公开(公告)号：US20170288693A1

公开(公告)日：2017-10-05

申请号：US15465305

申请日：2017-03-21

Applicant: STMicroelectronics International N.V.

Inventor： Ashish Sharma Kumar ,  Rajeev Jain ,  Chandrajit Debnath

IPC: H03M3/00 ,  H03M1/00

CPC classification number: H03M3/464 ,  H03M1/001 ,  H03M3/42 ,  H03M3/466 ,  H03M3/468 ,  H03M3/494

Abstract: A wide band continuous time delta-sigma modulator implements a time interleaved quantization processing operation. The modulator may provide for an inherent finite impulse response filtering in the feedback loop. Additionally, further finite impulse response filtering in each time interleaved feedback path may be provided.

公开(公告)号：US09775251B2

公开(公告)日：2017-09-26

申请号：US14957752

申请日：2015-12-03

Applicant: STMICROELECTRONICS INTERNATIONAL N.V.

Inventor： Patrik Arno ,  Eric Cirot

IPC: H05K3/32 ,  H03K17/16 ,  H02M1/08 ,  H02M3/158 ,  H02M7/483 ,  H02M1/00

CPC classification number: H05K3/32 ,  H02M1/08 ,  H02M3/1588 ,  H02M7/483 ,  H02M2001/0054 ,  H02M2007/4835 ,  H03K17/162 ,  Y02B70/1466 ,  Y02B70/1491

Abstract: A circuit is for controlling a power transistor of a DC/DC converter. The circuit may include first and second first transistors coupled in series between a first reference voltage and a control terminal of the power transistor, the first and second transistors defining a first junction node. The circuit may include third and fourth transistors coupled in series between the control terminal and a second reference voltage, the third and fourth transistors defining a second junction node. The first and second transistors may have a first conductivity type different from a second conductivity type of the third and fourth transistors. The circuit may include a capacitive element coupled between the first and second junction nodes.

公开(公告)号：US09762383B2

公开(公告)日：2017-09-12

申请号：US15160368

申请日：2016-05-20

Applicant: STMicroelectronics (Grenoble 2) SAS ,  STMicroelectronics International N.V.

Inventor： Julien Saade ,  Abdelaziz Goulahsen

IPC: H04L29/06 ,  H04L9/00 ,  H04L25/03

CPC classification number: H04L9/001 ,  H04L25/03 ,  H04L25/03866 ,  H04L2209/34

Abstract: A method for transmitting data in series includes producing a scrambled signal by applying a scrambling using a pseudo-random sequence to an incoming serial signal conveying the data and producing an outgoing serial signal. The scrambled signal is monitored to detect occurrences of one or more data patterns. In response to the detection of one or more occurrences, one or more actions are taken to protect data in the output signal.

公开(公告)号：US09755621B1

公开(公告)日：2017-09-05

申请号：US15162827

申请日：2016-05-24

Applicant: STMicroelectronics International N.V.

Inventor： Rohan Sinha ,  Vikas Rana

IPC: H03L5/00 ,  H03K3/356 ,  H03K19/0185

CPC classification number: H03K3/356113 ,  H03K19/018521

Abstract: A level shifting circuit operates at a high voltage level without stressing the transistors. The circuit has the ability to swing between large supply domains. Multiple output voltage levels are supported for the level shifted signal. Additionally, output nodes are stably driven to supply voltage levels that do not vary with respect to process corner and temperature.

公开(公告)号：US09728232B2

公开(公告)日：2017-08-08

申请号：US15167101

申请日：2016-05-27

Applicant: STMicroelectronics International N.V.

Inventor： Amit Chhabra

IPC: G11C5/14 ,  G05F1/46 ,  H03K3/037 ,  H03K5/08 ,  H03K17/22

CPC classification number: G11C5/148 ,  G05F1/46 ,  G05F1/465 ,  H03K3/0377 ,  H03K5/082 ,  H03K17/223

Abstract: When powering-up or exiting from a sleep mode, the ramping up of various supply voltage nodes may occur at different rates. Thus, in a dual-rail memory circuit, a first voltage rail may be at voltage before a second voltage rail. Such a transient state of operation may lead to current spikes that unnecessarily draw power and introduce undesired inefficiency. An internal sleep signal generation circuit in the dual-rail memory circuit precisely controls an internal sleep signal such that the transition from off or sleep mode to operating mode is set to assure that the supply voltage nodes are close enough to the at-voltage operating level before releasing the sleep mode.

公开(公告)号：US09705520B1

公开(公告)日：2017-07-11

申请号：US15380246

申请日：2016-12-15

Applicant: STMicroelectronics International N.V.

Inventor： Ashish Kumar ,  Chandrajit Debnath ,  Pratap Narayan Singh

IPC: H03M1/38 ,  H03M1/06 ,  H03M1/12 ,  H03M1/10

CPC classification number: H03M1/466 ,  H03M1/0863 ,  H03M1/1009 ,  H03M1/124 ,  H03M1/1245 ,  H03M1/164 ,  H03M1/38 ,  H03M1/44

Abstract: An embodiment circuit includes a first reference source configured to provide a first reference signal to an analog-to-digital convertor (ADC). The circuit also includes a filter coupled to an output of the first reference source and configured to filter the first reference signal to produce a filtered first reference signal. The circuit further includes a second reference source coupled to an output of the filter. The second reference source is configured to provide a second reference signal to the ADC, and the second reference signal is generated based on the filtered first reference signal.

公开(公告)号：US09698771B1

公开(公告)日：2017-07-04

申请号：US15203461

申请日：2016-07-06

Applicant: STMicroelectronics International N.V.

Inventor： Venkata Narayanan Srinivasan ,  Srinivas Dhulipalla

IPC: H03K17/22 ,  H03K5/19 ,  H03K19/20

CPC classification number: H03K17/223 ,  G01R31/2832 ,  G06F1/24 ,  G06F1/30 ,  H03K5/19 ,  H03K17/22 ,  H03K19/20

Abstract: A power management circuit includes both a power on reset (POR) circuit and a voltage monitoring circuit. Explicit testing of these circuits is accomplished by controlling voltages applied to the circuits and monitoring an output signal responsive to a logical combination of outputs from the POR circuit and voltage monitoring circuit. The applied voltages are controlled with respect to timing of application, fixing of voltages and varying of voltages in a manner where a certain one of the circuits for explicit test is isolated with change in logic state of the output signal being indicative of operation of that isolated circuit.

公开(公告)号：US09696351B2

公开(公告)日：2017-07-04

申请号：US14585357

申请日：2014-12-30

Applicant: STMICROELECTRONICS INTERNATIONAL N.V.

Inventor： Daljeet Kumar ,  Tapas Nandy ,  Surendra Kumar

IPC: G01R19/04 ,  G01R19/25

CPC classification number: G01R19/04 ,  G01R19/2503

Abstract: A data receiving device may include an envelope detector that may include first and second inputs configured to receive a differential input signal, a first pair of detectors coupled to the first input and configured to generate first and second detector outputs, and a second pair of detectors coupled to the second input and configured to generate third and fourth detector outputs. The envelope detector may also include a logic circuit configured to generate a reset based upon the first and third detectors. The data receiving device may also include a receiver circuit coupled to the envelope detector and configured to generate an output based upon the second and fourth detectors along with the reset, and a first bit detection circuit coupled to the receiver circuit.

公开(公告)号：US09685867B2

公开(公告)日：2017-06-20

申请号：US14466666

申请日：2014-08-22

Applicant: STMicroelectronics International N.V.

Inventor： Bohumil Janik

IPC: H02M3/158

CPC classification number: H02M3/1582

Abstract: A method supplies power from a power source to a load. The method includes, in a first mode, electrically coupling a step-down converter node of a step-down converter alternately to the power source via a conductive bypass path that bypasses a step-up converter and to ground. The step-up converter has an input electrically coupled to the power source and the step-down converter has an output electrically coupled to the load. The method further includes, in a second mode, coupling the step-down converter node alternately to the power source via the bypass path and to an output of the step-up converter.

公开(公告)号：US09654252B2

公开(公告)日：2017-05-16

申请号：US14931331

申请日：2015-11-03

Applicant: STMicroelectronics International N.V.

Inventor： Achraf Dhayni ,  Hussein Hijazi

IPC: H04B7/04 ,  H04L1/06 ,  H04L1/00 ,  H04L25/03 ,  H04B7/0413

CPC classification number: H04L1/0054 ,  H04B7/0413 ,  H04L1/0631 ,  H04L25/03197 ,  H04L25/03242 ,  H04L25/03961 ,  H04L2025/03414 ,  H04L2025/0342 ,  H04L2025/03426

Abstract: A receiver estimates a vector of emitted symbols over a MIMO transmission channel which is emitted by emitting antennas. The receiver receives a vector of received symbols on receiving antennas. Estimation of the vector of emitted symbols is made by calculating a metric associated with a criterion for each vector of a subset of all possible vectors of emitted symbols and selecting an estimation for said vector of emitted symbols as the vector of emitted symbols among said subset which minimizes said metric.