公开(公告)号：US20020186774A1

公开(公告)日：2002-12-12

申请号：US10075087

申请日：2002-02-11

Applicant: STMicroelectronics, S.r.I.

Inventor： Danilo Pau ,  Daniele Alfonso ,  Fabrizio Basso ,  Emiliano Piccinelli ,  Alessandro Cremonesi

IPC: H04N007/12

CPC classification number: H04N19/59 ,  H04N19/40 ,  H04N19/48 ,  H04N19/90

Abstract: A process and a system is described for generating an MPEG output bitstream starting from an MPEG input bitstream. The output bitstream has a resolution modified with respect to the resolution of the input bitstream. -In the input bitstream, first portions that substantially do not affect and second portions that do affect resolution variation are distinguished. The second portions are then subjected to a function of modification of the resolution obtained by filtering the second portions in a domain of the discrete cosine transform, and then are transferred to the output bitstream. A corresponding computer program product is also provided.

Abstract translation: 描述了从MPEG输入比特流开始生成MPEG输出比特流的过程和系统。 输出比特流具有关于输入比特流的分辨率修改的分辨率。 - 在输入比特流中，区分基本上不影响的第一部分和确实影响分辨率变化的第二部分。 然后对第二部分进行通过对离散余弦变换的域中的第二部分进行滤波而获得的分辨率的修改的功能，然后被传送到输出比特流。 还提供了相应的计算机程序产品。

公开(公告)号：US20020163848A1

公开(公告)日：2002-11-07

申请号：US10124494

申请日：2002-04-17

Applicant: STMicroelectronics S.r.I.

Inventor： Giuseppe GRASSO

IPC: G11C008/00

CPC classification number: G11C11/40615 ,  G11C7/1018 ,  G11C7/1045 ,  G11C11/406

Abstract: A random access memory (RAM) includes at least two memory banks. Each memory bank includes an array of dynamic random access memory (DRAM) cells, and self-refresh circuits for continuously submitting the DRAM cells to a refresh operation independent of the other memory banks. A first circuit selectively accesses one of the memory banks in response to an external access request. A second circuit suspends the refresh operation in the accessed memory bank while processing the external access request, and while the refresh operations in non-selected memory banks are not suspended.

Abstract translation: 随机存取存储器（RAM）包括至少两个存储体。 每个存储体包括动态随机存取存储器（DRAM）单元阵列和用于连续地将DRAM单元提交到独立于其它存储体的刷新操作的自刷新电路。 第一电路响应于外部访问请求选择性地访问存储体之一。 第二电路在处理外部访问请求时以及在未选择的存储体中的刷新操作不被暂停的情况下暂停在所访问的存储体中的刷新操作。

公开(公告)号：US20020163376A1

公开(公告)日：2002-11-07

申请号：US10050427

申请日：2002-01-15

Applicant: STMicroelectronics S.r.I.

Inventor： Domenico Pappalardo ,  Maurizio Gaibotti ,  Gaetano Palumbo ,  Antonino Conte ,  Stefano Lo Giudice

IPC: G05F001/10

CPC classification number: H02M3/07 ,  H02M2003/077

Abstract: A variable charge pump contains several individual simple charge pumps, each with a pumping capacitor and a switching mechanism. Additionally, a switching network is coupled to the individual charge pumps so that the different lines in the charge pump can be connected together in a serial mode or parallel mode (or mixed serial and parallel modes) to match the needs of the output load. The switching network is easily changed to provide the necessary driving capability as the needs of the output load changes.

Abstract translation: 可变电荷泵包含几个单独的简单电荷泵，每个具有泵浦电容器和开关机构。 此外，开关网络耦合到各个电荷泵，使得电荷泵中的不同线路可以以串行模式或并行模式（或混合串行和并行模式）连接在一起以匹配输出负载的需要。 随着输出负载的变化需要，开关网络容易改变以提供必要的驱动能力。

公开(公告)号：US20020152407A1

公开(公告)日：2002-10-17

申请号：US10010738

申请日：2001-11-05

Applicant: STMicroelectronics S.r.I.

Inventor： Michele Alia ,  Michele Carrano ,  Carmello Pistritto

IPC: G06F001/26

CPC classification number: G06F1/3243 ,  G06F1/3203 ,  G06F1/3287 ,  Y02D10/152 ,  Y02D10/171 ,  Y02D50/20

Abstract: A system-on-chip (SOC) includes a power down circuit. Within the SOC are several circuit blocks, each of them operating responsive to a local clock signal. A system clock is coupled to the circuit blocks for providing a system clock signal that functions as the local clock signal for selected circuit blocks. A power control manager provides a signal that at least partially determines whether the system clock will act as the local clock for some of the circuit blocks. Within the circuit blocks is a shutdown circuit that selectively prevents the system clock signal from functioning as the local clock signal in those circuit blocks that receive the shutdown signal, but the shutdown circuit only operates after both the signal to shutdown is received from the power control manager and after the circuit block has, in fact, shutdown.

Abstract translation: 片上系统（SOC）包括掉电电路。 SOC内部有几个电路块，每个电路块响应于本地时钟信号而工作。 系统时钟耦合到电路块，用于提供用作所选电路块的本地时钟信号的系统时钟信号。 功率控制管理器提供至少部分地确定系统时钟是否将用作一些电路块的本地时钟的信号。 在电路块内是关闭电路，其选择性地防止系统时钟信号作为接收关闭信号的那些电路块中的本地时钟信号起作用，但是关闭电路仅在从功率控制器接收到关闭信号 经理和电路块实际上已经关闭。

公开(公告)号：US20020140507A1

公开(公告)日：2002-10-03

申请号：US10075161

申请日：2002-02-13

Applicant: STMicroelectronics S.r.I.

Inventor： Pietro Filoramo ,  Tiziano Chiarillo

IPC: H03F003/45

CPC classification number: H03G7/08

Abstract: A variable gain amplifier is described which comprises a first device to which a first control signal (Vc, Vc1) is applied so that the gain (Ai1, Ai) of an output signal (iout, io) of the first device (11, 22, Q45-Q48) with respect to a first input signal (in, i1, ir) is a function of the exponential type of the first control signal (Vc, Vc1). The amplifier comprises a feedback network (25, Q51-Q58) connected between an output terminal and an input terminal of the first device (22, Q45-Q48) so as to assure that the gain (Ai) in decibel of the first device (22, Q45-Q48) is a linear function of the first control signal (Vc1). (FIG. 2)

Abstract translation: 描述了一种可变增益放大器，其包括第一装置，第一装置施加第一控制信号（Vc，Vc1），使得第一装置（11,22）的输出信号（iout，io）的增益（Ai1，Ai） 相对于第一输入信号（in，i1，ir），Q45-Q48是第一控制信号（Vc，Vc1）的指数类型的函数。 放大器包括连接在第一装置（22，Q45-Q48）的输出端子和输入端子之间的反馈网络（25，Q51-Q58），以便确保第一装置的分贝的增益（Ai）（ 22，Q45-Q48）是第一控制信号（Vc1）的线性函数。 （图2）

公开(公告)号：US20020130334A1

公开(公告)日：2002-09-19

申请号：US10036088

申请日：2001-12-28

Applicant: STMicroelectronics, S.r.I.

Inventor： Roberto Gastaldi ,  Gianbattsista Lo Giudice ,  Marco Pasotti ,  Federico Pio

IPC: H01L031/072

CPC classification number: G11C16/102

Abstract: An electrically-modifiable, non-volatile, semiconductor memory comprising a plurality of user memory locations which can be addressed individually from outside the memory in order to read and to modify the data held therein is characterized in that, for each user memory location, there is a corresponding pair of physical memory locations in the memory, which assume, alternatively, the functions of an active memory location and of a non-active memory location, the active memory location containing a previously-written datum and the non-active memory location being available for the writing of a new datum to replace the previously-written datum, so that, upon a request to replace the previous datum with the new datum, the previous datum is kept in the memory until the new datum has been written.

Abstract translation: 一种可电气修改的非易失性半导体存储器，其包括多个用户存储器位置，其可以从存储器外部单独寻址以便读取和修改其中保存的数据，其特征在于，对于每个用户存储器位置， 存储器中的对应物理存储器位置对，其替代地假设有效存储器位置和非活动存储器位置的功能，所述活动存储器位置包含预先写入的数据和非活动存储器位置 可用于写入新的数据以替换以前写入的数据，以便在要求使用新数据替换以前的数据时，先前的数据保存在存储器中，直到新的数据被写入。

公开(公告)号：US20020123195A1

公开(公告)日：2002-09-05

申请号：US10006778

申请日：2001-11-05

Applicant: STMicroelectronics S.r.I

Inventor： Ferruccio Frisina ,  Giuseppe Ferla ,  Salvatore Rinaudo

IPC: H01L021/336

CPC classification number: H01L29/7802 ,  H01L29/0847 ,  H01L29/66712

Abstract: A MOS-gated power device includes a plurality of elementary functional units, each elementary functional unit including a body region of a first conductivity type formed in a semiconductor material layer of a second conductivity type having a first resistivity value. Under each body region a respective lightly doped region of the second conductivity type is provided having a second resistivity value higher than the first resistivity value.

Abstract translation: MOS门控功率器件包括多个基本功能单元，每个基本功能单元包括形成在具有第一电阻率值的第二导电类型的半导体材料层中的第一导电类型的体区。 在每个体区下方提供具有高于第一电阻率值的第二电阻率值的第二导电类型的相应轻掺杂区。

公开(公告)号：US20020113247A1

公开(公告)日：2002-08-22

申请号：US10072817

申请日：2002-02-08

Applicant: STMicroelectronics S.r.I.

Inventor： Angelo Magri ,  Leonardo Fragapane

IPC: H01L029/76

CPC classification number: H01L24/06 ,  H01L23/49562 ,  H01L24/48 ,  H01L24/49 ,  H01L25/071 ,  H01L2224/02166 ,  H01L2224/04042 ,  H01L2224/05553 ,  H01L2224/05624 ,  H01L2224/05644 ,  H01L2224/0603 ,  H01L2224/32145 ,  H01L2224/32245 ,  H01L2224/48091 ,  H01L2224/48137 ,  H01L2224/48139 ,  H01L2224/48247 ,  H01L2224/48472 ,  H01L2224/4903 ,  H01L2224/49051 ,  H01L2224/73265 ,  H01L2924/00014 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01015 ,  H01L2924/01022 ,  H01L2924/01023 ,  H01L2924/01024 ,  H01L2924/01028 ,  H01L2924/01079 ,  H01L2924/01093 ,  H01L2924/1305 ,  H01L2924/13055 ,  H01L2924/13091 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/05599

Abstract: A method of manufacturing an electronic structure, which structure comprises a first power device and a second unidirectional device, both integrated in the same protective package. The first device having at least first and second electrodes of the first device, with said first electrode of the first device being attached to the package. The second device having first and second electrodes of the second device, wherein the first electrode of the second device is superposed on the second electrode of the first device and connected electrically to the second electrode of the first device.

Abstract translation: 一种制造电子结构的方法，该结构包括集成在同一保护封装中的第一电力装置和第二单向装置。 所述第一装置具有所述第一装置的至少第一和第二电极，所述第一装置的所述第一电极附接到所述包装。 第二装置具有第二装置的第一和第二电极，其中第二装置的第一电极重叠在第一装置的第二电极上并与第一装置的第二电极电连接。

公开(公告)号：US20020070464A1

公开(公告)日：2002-06-13

申请号：US09997995

申请日：2001-11-30

Applicant: STMicroelectronics S.r.I.

Inventor： Giovanni Frezza

IPC: H01L023/29

CPC classification number: H01L21/565 ,  H01L2224/32245 ,  H01L2224/48137 ,  H01L2224/48247 ,  H01L2224/73265 ,  H01L2924/1815 ,  H01L2924/00

Abstract: A method for forming by molding a plastic protective package for an electronic integrated circuit that includes an electronic device activated from the outside of said protective package. The method includes: dispensing a covering layer of elastic material on a portion of said electronic device; shaping said covering layer to form a projecting portion from a surface of said electronic device; molding said electronic integrated circuit in said plastic protective package using a mold including at least a half-mold abutting against said projecting portion; and obtaining a hole or a window formed in alignment with said projecting portion in said protective package.

Abstract translation: 一种用于通过模制用于电子集成电路的塑料保护包装形成的方法，该电子集成电路包括从所述保护包装的外部激活的电子装置。 该方法包括：在所述电子设备的一部分上分配弹性材料的覆盖层; 成形所述覆盖层以从所述电子设备的表面形成突出部分; 使用包括至少半个模具抵靠所述突出部分的模具将所述电子集成电路模制在所述塑料保护包装中; 并且获得与所述保护包装中的所述突出部分对准形成的孔或窗口。

公开(公告)号：US20020057604A1

公开(公告)日：2002-05-16

申请号：US09953070

申请日：2001-09-13

Applicant: STMicroelectronics S.r.I.

Inventor： Osama Khouri ,  Alessandro Manstretta ,  Guido Torelli

IPC: G11C007/00

CPC classification number: G11C7/062 ,  G11C16/28 ,  G11C2207/063

Abstract: A reading circuit for semiconductor non-volatile memories connected to at least one selected cell and at least one reference cell, the circuit including current/voltage conversion circuits receiving at the input thereof a first current flowing through the selected cell and a second current flowing through the reference cell and providing respectively on a first circuit node a first selected cell voltage and on a second node a second reference cell voltage, as well as at least one differential amplifier, connected at the input of the first and the second nodes and having an output terminal effective to provide a logic signal correlated to the selected cell information. The reading circuit also includes at least a first voltage-controlled discharge switch circuit connected at the input of the first node and to a voltage reference, a second voltage-controlled discharge switch circuit connected at the input of the second node and to the voltage reference, as well as a first and a second voltage comparator circuits receiving at the input thereof the first selected cell voltage and the second reference cell voltage. Moreover, advantageously according to the invention, the comparator circuits are effective to control the switch circuits.

Abstract translation: 一种用于连接到至少一个选定单元和至少一个参考单元的半导体非易失性存储器的读取电路，所述电路包括电流/电压转换电路，其在输入端接收流过选定单元的第一电流和流过所选单元的第二电流 所述参考单元并且分别在第一电路节点上提供第一选择的单元电压，并在第二节点上提供第二参考单元电压以及至少一个差分放大器，所述差分放大器连接在所述第一和第二节点的输入端，并且具有 输出端有效地提供与所选择的单元信息相关的逻辑信号。 读取电路还包括至少连接在第一节点的输入端和电压基准的第一压控放电开关电路，连接在第二节点的输入端的第二压控放电开关电路和电压基准 以及在其输入端接收第一选定单元电压和第二参考单元电压的第一和第二电压比较器电路。 此外，有利地根据本发明，比较器电路有效地控制开关电路。