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公开(公告)号：US20190190381A1
公开(公告)日：2019-06-20
申请号：US16222366
申请日：2018-12-17
Applicant: STMicroelectronics (Grenoble 2) SAS
Inventor： David Chesneau , Francois Amiard
CPC classification number: H02M3/158 , H02M1/08 , H02M3/155 , H02M2003/1555
Abstract: A method includes switching a switching circuit of the switched-mode power supply in a synchronous mode by turning on and off switches of the switching circuit in synchrony with a clock signal, wherein the switching circuit is coupled to an inductive element, and wherein the synchronous mode comprises a charging phase and a discharging phase; switching the switching circuit in an asynchronous mode by turning on and off switches of the switching circuit without being synchronized with the clock signal, wherein the asynchronous mode comprises a charging phase and a discharging phase; charging the inductive element during the charging phase of the synchronous mode; discharging the inductive element during the discharging phase of the synchronous mode; charging the inductive element during the charging phase of the asynchronous mode; and discharging the inductive element during the discharging phase of the asynchronous mode.
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公开(公告)号：US20190189859A1
公开(公告)日：2019-06-20
申请号：US16218906
申请日：2018-12-13
Applicant: STMICROELECTRONICS (GRENOBLE 2) SAS
Inventor： Jean-Michel RIVIERE , Romain COFFY , Karine SAXOD
IPC: H01L33/48 , H01L33/00 , H01L33/58 , H01L31/18 , H01L31/12 , H01L31/0232 , H01L31/0203 , H05K5/03
CPC classification number: H01L33/483 , H01L31/0203 , H01L31/02327 , H01L31/12 , H01L31/162 , H01L31/18 , H01L33/005 , H01L33/58 , H05K5/03
Abstract: A cover for an electronic circuit package, including an element having peripheral portions housed in an inner groove of a through opening.
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333.发明申请公开(公告)号：US20190172795A1
公开(公告)日：2019-06-06
申请号：US16210149
申请日：2018-12-05
Inventor： Eric SABOURET , Krysten ROCHEREAU , Olivier HINSINGER , Flore PERSIN-CRELEROT
IPC: H01L23/00 , H05K3/34 , H01L21/66 , H01L23/498
Abstract: An integrated circuit includes a solder pad which includes, in a superposition of metallization levels, an underlying structure formed by a network of first regular metal tracks that are arranged for reinforcing the mechanical strength of the underlying structure and electrically connecting between an upper metallization level and a lower metallization level of the underlying structure. The underlying structure further includes a detection electrical path formed by second metal tracks passing between the first metal tracks in the metallization levels, the detection electrical path having an input terminal and an output terminal. Electrical sensing of the detection electrical path is made to supply a measurement which is indicative of the presence of cracks in the underlying structure.
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334.发明申请公开(公告)号：US20190088562A1
公开(公告)日：2019-03-21
申请号：US16133065
申请日：2018-09-17
Inventor： Jerome LOPEZ , Roseanne DUCA
IPC: H01L23/10 , H01L23/498 , H01L21/50 , H01L23/31
CPC classification number: H01L23/10 , H01L21/50 , H01L23/3121 , H01L23/49838
Abstract: A support substrate has a face above which at least one electronic component is fixed. A peripheral area of the face includes an annular local metal layer. An encapsulating cover for the electronic component includes a peripheral wall having an end edge that is mounted above the peripheral area. The annular metal local layer includes, at the periphery thereof, a series of spaced-apart teeth with notches formed therebetween. The teeth extend as far as the peripheral edge of the support substrate.
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公开(公告)号：US20190067180A1
公开(公告)日：2019-02-28
申请号：US16110121
申请日：2018-08-23
Inventor： David AUCHERE , Laurent SCHWARZ , Deborah COGONI , Eric SAUGIER
IPC: H01L23/498 , H01L23/31 , H01L23/13 , H01L23/00
CPC classification number: H01L23/49838 , H01L21/561 , H01L21/78 , H01L23/13 , H01L23/3128 , H01L23/49822 , H01L23/49833 , H01L23/5389 , H01L24/00 , H01L24/16 , H01L24/97 , H01L2224/16227 , H01L2224/16235 , H05K1/185 , H05K2201/10621 , H05K2201/10636
Abstract: An electronic device includes a support wafer, an electronic chip and an encapsulating block for the electronic chip above the support wafer. The support wafer is provided with a first network of electrical connections and a second network of electrical connections formed solely by tracks. First electrical connection elements are interposed between first front electrical contacts of the electronic chip and rear electrical contacts of the first network. Second electrical connection elements are interposed between second front electrical contacts of the electronic chip and internal electrical contact zones of the tracks of the second network. The first network includes front external electrical contacts and the tracks exhibiting external electrical contact zones.
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Patent Agency Ranking
公开(公告)号：US20190064859A1
公开(公告)日：2019-02-28
申请号：US16111933
申请日：2018-08-24
Applicant: STMicroelectronics (Grenoble 2) SAS
Inventor： Christophe Lorin
IPC: G05F1/46
Abstract: A device can be used for managing for managing the supply voltage on an output power supply pin of a USB Type-C source device that includes an AC-to-DC power converter for delivering the supply voltage. The source device is capable of supplying power to a receiver device. A power supply controller includes a first circuit configured to deliver a signal for discharging a capacitive network coupled to the power converter and also includes a second circuit configured to deliver, at the same time as the discharge signal, a new setpoint signal, corresponding to the new voltage delivered, to a control input of the power converter. A delay element is coupled between an output of the second circuit and the control input.
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公开(公告)号：US10170513B2
公开(公告)日：2019-01-01
申请号：US15713639
申请日：2017-09-23
Applicant: Commissariat à l'Energie Atomique et aux Energies Alternatives , STMICROELECTRONICS (CROLLES 2) SAS , STMICROELECTRONICS (GRENOBLE 2) SAS
Inventor： Yvon Cazaux , François Roy , Marie Guillon , Arnaud Laflaquiere
IPC: H01L27/146 , H01L27/12
Abstract: An image sensor arranged inside and on top of a semi-conductor substrate having a front surface and a rear surface, the sensor including a plurality of pixels, each including: a photosensitive area, a reading area, and a storage area extending between the photosensitive area and the reading area; a vertical insulated electrode including an opening of transfer between the photosensitive area and the storage area; and at least one insulation element among the following: a) a layer of an insulating material extending under the surface of the photosensitive area and of the storage area and having its front surface in contact with the rear surface of the electrode; and b) an insulating wall extending vertically in the opening, or under the opening.
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公开(公告)号：US20180375637A1
公开(公告)日：2018-12-27
申请号：US15898816
申请日：2018-02-19
Applicant: STMicroelectronics (Grenoble 2) SAS
Inventor： Etienne Cesar
Abstract: In an embodiment, a clock synchronizing circuit includes: a phase comparator including a first circuit having a first input configured to receive a data signal; and a second circuit. The first circuit is configured to detect edges of the data signal. The second circuit includes a clock generator configured to generate a clock signal with adjustable frequency, where the phase comparator is configured to compare, after detecting an edge of the data signal, an edge of the data signal with an edge of the clock signal, and where the second circuit is configured to modify a frequency of the clock signal as a function of an output signal of the phase comparator.
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公开(公告)号：US10114687B2
公开(公告)日：2018-10-30
申请号：US14949378
申请日：2015-11-23
Applicant: STMicroelectronics (Grenoble 2) SAS
Inventor： Gilles Ries , Abdelaziz Goulahsen
Abstract: A method of verifying integrity of communications between a master circuit and a slave circuit includes updating a first cyclic multibit signature based on each transaction sent by the master circuit to the slave circuit. A second cyclic multibit signature is updated based on each transaction received by the slave circuit. One or more bits based on the second cyclic multibit signature are compared with corresponding bits based on the first cyclic multibit signature, with a number of the one or more bits being less than a total number of bits of the second cyclic signature. Error conditions are detected and responded based on the comparing.
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公开(公告)号：US20180241395A1
公开(公告)日：2018-08-23
申请号：US15956292
申请日：2018-04-18
Applicant: STMicroelectronics (Grenoble 2) SAS
Inventor： Thierry Masson , Pawel Fiedorow
IPC: H03K19/018 , H03K17/693 , H01L29/66 , G06F11/20 , H01L29/06 , H03K17/16
CPC classification number: H03K19/01843 , G06F11/20 , H01L29/0661 , H01L29/66659 , H03K17/005 , H03K17/063 , H03K17/165 , H03K17/6874 , H03K17/693 , H03K2217/0054 , H03K2217/0081
Abstract: An analog multiplexer includes inputs and one output. A switching circuit is coupled between each input and the output. Each switching circuit includes an NMOS switching module, having an on state and an off state, and a control module supplied by a first supply voltage and operating to reduce leakage currents of the NMOS switching module when in the off state. The control module further operates to make the first NMOS switching module bidirectional irrespective of voltages present at the input and at the output.
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