公开(公告)号：US20160187483A1

公开(公告)日：2016-06-30

申请号：US14674650

申请日：2015-03-31

Applicant: STMICROELECTRONICS PTE LTD

Inventor： Jing-En LUAN ,  Jerome TEYSSEYRE

IPC: G01S17/02 ,  H01L31/167 ,  H01L31/0232 ,  G01S7/481 ,  H01L31/02 ,  H01S5/022 ,  H01S5/183 ,  H01L25/16 ,  H01L31/18

CPC classification number: G01S17/026 ,  G01S7/4813 ,  H01L25/167 ,  H01L31/173 ,  H01L2224/16 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2224/92227 ,  H01L2224/97 ,  H01L2924/181 ,  H01L2924/00014 ,  H01L2924/00012 ,  H01L2924/00

Abstract: A proximity sensor includes a printed circuit board substrate, a semiconductor die, electrical connectors, a lens, a light emitting assembly, and an encapsulating layer. The semiconductor die is positioned over the printed circuit board substrate with its upper surface facing away from the printed circuit board substrate. Each of the electrical connectors is in electrical communication with a contact pad of the semiconductor die and a respective contact pad of the printed circuit board substrate. The lens is positioned over a sensor area of the semiconductor die. The light emitting assembly includes a light emitting device having a light emitting area, a lens positioned over the light emitting area, and contact pads facing the printed circuit board substrate. The encapsulating layer is positioned on the printed circuit board substrate, at least one of the electrical connectors, the semiconductor die, the lens, and the light emitting assembly.

Abstract translation: 接近传感器包括印刷电路板基板，半导体管芯，电连接器，透镜，发光组件和封装层。 半导体管芯位于印刷电路板基板上方，其上表面背离印刷电路板基板。 每个电连接器与半导体管芯的接触焊盘和印刷电路板基板的相应接触焊盘电连通。 透镜位于半导体管芯的传感器区域上方。 发光组件包括具有发光区域的发光器件，位于发光区域上方的透镜以及面向印刷电路板衬底的接触焊盘。 封装层位于印刷电路板基板上，至少一个电连接器，半导体管芯，透镜和发光组件。

公开(公告)号：US20160184938A1

公开(公告)日：2016-06-30

申请号：US14586678

申请日：2014-12-30

Applicant: STMICROELECTRONICS PTE LTD

Inventor： Yonggang JIN ,  Yun LIU

IPC: B23K35/36 ,  B23K35/02

CPC classification number: B23K35/3618 ,  B23K35/0227 ,  B23K35/0266 ,  B23K35/3613

Abstract: The present disclosure is directed to a solder wire that includes a core having both a rosin flux and a thermoset material. The solder wire being configured to provide an oxide removing rosin flux to an electrical component, a solder alloy to the electrical component, and a protective layer to the solder alloy in a single soldering step.

Abstract translation: 本公开涉及一种焊丝，其包括具有松香焊剂和热固性材料两者的芯。 所述焊丝被配置为在单个焊接步骤中提供氧化物去除松香助焊剂到电组件，到电组件的焊料合金以及焊料合金的保护层。

公开(公告)号：US20160118289A1

公开(公告)日：2016-04-28

申请号：US14986130

申请日：2015-12-31

Applicant: STMicroelectronics Pte Ltd

Inventor： Calvin LEUNG ,  Olivier LE NEEL

IPC: H01L21/683 ,  H01L29/66 ,  H01L21/56 ,  H01L23/498 ,  H01L23/00 ,  H01L27/105 ,  H01L21/48 ,  H01L21/768 ,  H01L49/02

CPC classification number: H01L21/6835 ,  H01L21/4846 ,  H01L21/568 ,  H01L21/76895 ,  H01L23/3135 ,  H01L23/49822 ,  H01L23/4985 ,  H01L23/5389 ,  H01L24/20 ,  H01L27/0629 ,  H01L27/1052 ,  H01L28/60 ,  H01L29/6675 ,  H01L2221/68345 ,  H01L2221/68359 ,  H01L2224/18 ,  H01L2924/0002 ,  H01L2924/00

Abstract: An electronic device is formed by depositing polyimide on a glass substrate. A conductive material is deposited on the polyimide and patterned to form electrodes and signal traces. Remaining portions of the electronic device are formed on the polyimide. A second polyimide layer is then formed on the first polyimide layer. The glass substrate is then removed, exposing the electrodes and the top surface of the electronic device.

公开(公告)号：US20160104738A1

公开(公告)日：2016-04-14

申请号：US14741561

申请日：2015-06-17

Applicant: STMICROELECTRONICS PTE LTD

Inventor： Jing-En LUAN

IPC: H01L27/146

CPC classification number: H01L27/14636 ,  H01L27/14618 ,  H01L27/14625 ,  H01L27/14685 ,  H01L2224/48095 ,  H01L2224/73265

Abstract: An image sensing device may include an interconnect layer, an image sensor IC coupled to the interconnect layer and having an image sensing surface, and an IR filter aligned with the image sensing surface opposite the interconnect layer. The image sensing device may include a flexible interconnect layer aligned with the interconnect layer and having a flexible substrate extending laterally outwardly from the interconnect layer, and electrically conductive traces on the flexible substrate. The image sensing device may also include solder bodies coupling the interconnect layer and the flexible interconnect layer and also defining a gap between the interconnect layer and the flexible interconnect layer.

Abstract translation: 图像感测装置可以包括互连层，耦合到互连层并具有图像感测表面的图像传感器IC和与互连层相对的图像感测表面对准的IR滤光器。 图像感测装置可以包括与互连层对准的柔性互连层，并且具有从互连层横向向外延伸的柔性衬底以及柔性衬底上的导电迹线。 图像感测装置还可以包括耦合互连层和柔性互连层并且还限定互连层和柔性互连层之间的间隙的焊料体。

公开(公告)号：US20160093490A1

公开(公告)日：2016-03-31

申请号：US14957141

申请日：2015-12-02

Applicant: STMICROELECTRONICS PTE LTD

Inventor： CHONG JIEH CHEW

IPC: H01L21/02 ,  H01L21/033

CPC classification number: H01L21/02252 ,  H01L21/02129 ,  H01L21/02274 ,  H01L21/02321 ,  H01L21/02334 ,  H01L21/0234 ,  H01L21/033 ,  H01L21/31144

Abstract: A method for making semiconductor devices may include forming a phosphosilicate glass (PSG) layer on a semiconductor wafer, with the PSG layer having a phosphine residual surface portion. The method may further include exposing the phosphine residual surface portion to a reactant plasma to integrate at least some of the phosphine residual surface portion into the PSG layer. The method may additionally include forming a mask layer on the PSG layer after the exposing.

公开(公告)号：US20160035590A1

公开(公告)日：2016-02-04

申请号：US14450554

申请日：2014-08-04

Applicant: STMicroelectronics Pte Ltd

Inventor： Yonggang Jin

IPC: H01L21/56 ,  H01L25/07 ,  H01L21/78 ,  H01L23/498 ,  H01L25/00 ,  H01L21/48

CPC classification number: H01L21/563 ,  H01L21/4803 ,  H01L21/4853 ,  H01L21/486 ,  H01L21/561 ,  H01L21/565 ,  H01L21/568 ,  H01L21/78 ,  H01L23/3128 ,  H01L23/49811 ,  H01L23/49827 ,  H01L23/49838 ,  H01L23/49861 ,  H01L24/13 ,  H01L24/16 ,  H01L24/32 ,  H01L24/73 ,  H01L24/97 ,  H01L25/0655 ,  H01L25/0657 ,  H01L25/072 ,  H01L25/18 ,  H01L25/50 ,  H01L2224/131 ,  H01L2224/16145 ,  H01L2224/16235 ,  H01L2224/16238 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/97 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2924/15311 ,  H01L2924/157 ,  H01L2924/15788 ,  H01L2924/3511 ,  H01L2924/014 ,  H01L2224/81 ,  H01L2224/83

Abstract: One or more embodiments are directed to a system-in-package (SiP) that includes a plurality of semiconductor chips and an interposer that that are molded in an encapsulation layer together. That is, a single processing step may be used to encapsulate the semiconductor chips and the interposer in the encapsulation layer. Furthermore, prior to setting or curing, the encapsulation layer is able to flow between the semiconductor chips and the interposer to provide further mechanical support for the semiconductor chips. Thus, the process for forming the SiP is reduced, resulting in a faster processing time and a lower cost. Additionally, one or more embodiments described herein reduce or eliminate warpage of the interposer.

Abstract translation: 一个或多个实施例涉及包括多个半导体芯片的系统级封装（SiP）和在封装层中一起模塑的插入器。 也就是说，可以使用单个处理步骤来将半导体芯片和插入器封装在封装层中。 此外，在固化或固化之前，封装层能够在半导体芯片和插入件之间流动，以为半导体芯片提供进一步的机械支撑。 因此，形成SiP的工艺减少，加工时间更短，成本更低。 另外，本文所述的一个或多个实施例减少或消除插入件的翘曲。

公开(公告)号：US09252030B1

公开(公告)日：2016-02-02

申请号：US14450554

申请日：2014-08-04

Applicant: STMicroelectronics Pte Ltd

Inventor： Yonggang Jin

IPC: H01L23/49 ,  H01L21/56 ,  H01L25/00 ,  H01L21/48 ,  H01L21/78 ,  H01L23/498 ,  H01L25/07

CPC classification number: H01L21/563 ,  H01L21/4803 ,  H01L21/4853 ,  H01L21/486 ,  H01L21/561 ,  H01L21/565 ,  H01L21/568 ,  H01L21/78 ,  H01L23/3128 ,  H01L23/49811 ,  H01L23/49827 ,  H01L23/49838 ,  H01L23/49861 ,  H01L24/13 ,  H01L24/16 ,  H01L24/32 ,  H01L24/73 ,  H01L24/97 ,  H01L25/0655 ,  H01L25/0657 ,  H01L25/072 ,  H01L25/18 ,  H01L25/50 ,  H01L2224/131 ,  H01L2224/16145 ,  H01L2224/16235 ,  H01L2224/16238 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/97 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2924/15311 ,  H01L2924/157 ,  H01L2924/15788 ,  H01L2924/3511 ,  H01L2924/014 ,  H01L2224/81 ,  H01L2224/83

Abstract: One or more embodiments are directed to a system-in-package (SiP) that includes a plurality of semiconductor chips and an interposer that that are molded in an encapsulation layer together. That is, a single processing step may be used to encapsulate the semiconductor chips and the interposer in the encapsulation layer. Furthermore, prior to setting or curing, the encapsulation layer is able to flow between the semiconductor chips and the interposer to provide further mechanical support for the semiconductor chips. Thus, the process for forming the SiP is reduced, resulting in a faster processing time and a lower cost. Additionally, one or more embodiments described herein reduce or eliminate warpage of the interposer.

Abstract translation: 一个或多个实施例涉及包括多个半导体芯片的系统级封装（SiP）和在封装层中一起模塑的插入器。 也就是说，可以使用单个处理步骤来将半导体芯片和插入器封装在封装层中。 此外，在固化或固化之前，封装层能够在半导体芯片和插入件之间流动，以为半导体芯片提供进一步的机械支撑。 因此，形成SiP的工艺减少，加工时间更短，成本更低。 此外，本文所述的一个或多个实施例减少或消除插入件的翘曲。

公开(公告)号：US09236243B2

公开(公告)日：2016-01-12

申请号：US14151188

申请日：2014-01-09

Applicant: STMICROELECTRONICS PTE LTD

Inventor： ChongJieh Chew

IPC: H01L21/00 ,  H01L21/02 ,  H01L21/033

CPC classification number: H01L21/02252 ,  H01L21/02129 ,  H01L21/02274 ,  H01L21/02321 ,  H01L21/02334 ,  H01L21/0234 ,  H01L21/033 ,  H01L21/31144

Abstract: A method for making semiconductor devices may include forming a phosphosilicate glass (PSG) layer on a semiconductor wafer, with the PSG layer having a phosphine residual surface portion. The method may further include exposing the phosphine residual surface portion to a reactant plasma to integrate at least some of the phosphine residual surface portion into the PSG layer. The method may additionally include forming a mask layer on the PSG layer after the exposing.

Abstract translation: 制造半导体器件的方法可以包括在半导体晶片上形成磷硅玻璃（PSG）层，其中PSG层具有磷化氢残留表面部分。 该方法可以进一步包括将磷化氢残余表面部分暴露于反应物等离子体以将至少一些磷化氢残余表面部分整合到PSG层中。 该方法还可以包括在曝光之后在PSG层上形成掩模层。

公开(公告)号：US09164674B2

公开(公告)日：2015-10-20

申请号：US13852478

申请日：2013-03-28

Applicant: STMICROELECTRONICS ASIA PACIFIC PTE LTD. ,  STMICROELECTRONICS PTE LTD.

Inventor： Chee Yu Ng ,  Jo Wang ,  Ravi Bhatia

IPC: G06F3/041 ,  G06F3/0488 ,  G06F3/044 ,  A63F13/20 ,  A63F13/42 ,  A63F13/2145

CPC classification number: G06F3/0488 ,  A63F13/20 ,  A63F13/2145 ,  A63F13/42 ,  G06F3/044

Abstract: A touch controller is coupled to a touch screen and detects a first gesture at a first point on the touch screen. The first gesture includes physical contact of the touch screen by a user device at the first point. The touch controller detects a second gesture that is associated with movement of the user device from the first point to a second point on the touch screen. The second gesture includes detecting movement of the user device within a sensing range from the first point to the second point. The sensing range corresponds to an orthogonal distance from a surface of the touch screen. The touch controller detects a third gesture at the second touch point. The third gesture includes physical contact of the touch screen at the second touch point. Upon detecting the first, second and third gestures the touch controller performs a corresponding action.

Abstract translation: 触摸控制器耦合到触摸屏并且在触摸屏上的第一点检测第一手势。 第一姿态包括用户设备在第一点处的触摸屏的物理接触。 触摸控制器检测与用户设备从第一点移动到触摸屏上的第二点相关联的第二手势。 第二手势包括在从第一点到第二点的感测范围内检测用户设备的移动。 感测范围对应于从触摸屏的表面的正交距离。 触摸控制器在第二触摸点检测第三手势。 第三手势包括触摸屏在第二触摸点处的物理接触。 当检测到第一，第二和第三手势时，触摸控制器执行相应的动作。

公开(公告)号：US20150235929A1

公开(公告)日：2015-08-20

申请号：US14615673

申请日：2015-02-06

Applicant: STMicroelectronics (Malta) Ltd ,  STMicroelectronics S.r.I. ,  STMicroelectronics Pte Ltd

Inventor： Roseanne Duca ,  Valter Motta ,  Xueren Zhang ,  Kim-Yong Goh

IPC: H01L23/495

CPC classification number: H01L23/49568 ,  H01L23/4334 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/48464 ,  H01L2924/18301 ,  H01L2924/00014

Abstract: An electronic device includes an integrated circuit chip mounted to a heat slug. The heat slug has a peripheral region having first thickness along a first direction, the peripheral region surrounding a recess region (having a second, smaller, thickness along the first direction) that defines a chip mounting surface along a second direction perpendicular to the first direction. The recess region defines side borders and a nook extends into the heat slug along the side borders. An insulating body embeds the integrated circuit one chip and heat slug. Material of the insulating body fills the nook.

Abstract translation: 一种电子设备包括安装在散热片上的集成电路芯片。 散热片具有沿着第一方向具有第一厚度的周边区域，周边区域围绕沿着垂直于第一方向的第二方向限定芯片安装表面的凹陷区域（具有沿着第一方向的第二较小厚度） 。 凹槽区域限定侧面边界，并且角部沿着侧边缘延伸到热塞中。 绝缘体嵌入集成电路一芯片和散热片。 绝缘体的材料填充角。