公开(公告)号：US20050006722A1

公开(公告)日：2005-01-13

申请号：US10853015

申请日：2004-05-25

Applicant: Romina Zonca

Inventor： Romina Zonca

IPC: H01L21/768 ,  H01L45/00 ,  G11B7/24 ,  H01L21/20 ,  H01L21/469 ,  H01L23/52 ,  H01L29/00

CPC classification number: H01L45/06 ,  H01L21/76841 ,  H01L45/1233 ,  H01L45/126 ,  H01L45/16

Abstract: The process for forming a film of TiSiN includes the following sequence of steps: deposition of a TiN film at medium temperature, for example, 300-450° C., by thermal decomposition of a metallorganic precursor, for example TDMAT (Tetrakis Dimethylamino Titanium); exposition to a silicon releasing gas, such as silane (SiH4) and dichlorosilane (SiH2Cl2) at 10-90 sccm—standard cube centimeters per minute—for a quite long time, for example, longer than 10 s but less than 90 s, preferably about 40 s; exposition to a H2/N2 plasma at 200-800 sccm, for 10-90 s, preferably about 40 s.

Abstract translation: 用于形成TiSiN膜的方法包括以下步骤顺序：通过金属有机前体（例如TDMAT（四甲基氨基钛））的热分解在中等温度例如300-450℃下沉积TiN膜， ; 以10-90sccm - 标准立方厘米每分钟的硅烷（SiH 4）和二氯硅烷（SiH 2 Cl 2）曝光相当长的时间，例如长于10秒但小于90秒的硅释放气体，优选 约40秒; 以200-800sccm显示H2 / N2等离子体，10-90秒，优选约40秒。

公开(公告)号：US20040268275A1

公开(公告)日：2004-12-30

申请号：US10850834

申请日：2004-05-21

Applicant: STMicroelectronics S.r.I.

Inventor： Paolo Cappelletti ,  Alfonso Maurelli

IPC: H01L021/44 ,  G06F017/50

CPC classification number: H01L22/34 ,  G01R31/2853 ,  G01R31/2884 ,  G11C29/02 ,  G11C29/022 ,  G11C29/025 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A test chip performs measurements to evaluate the performances of interconnects. In particular, the statistical failure distribution, the electromigration and the leakage current are measured. An algorithm detects a via failure at any of the available n metal layers. The test chip includes a ROM memory array. The vias to be measured are formed in the columns of the array. Via or contact failures are detected by forcing a predetermined current through both an array column and a reference column. The failure analysis is obtained by comparing the resulting voltage drops.

Abstract translation: 测试芯片执行测量以评估互连的性能。 特别地，测量统计失效分布，电迁移和漏电流。 算法检测任何可用的n个金属层的通孔故障。 测试芯片包括ROM存储器阵列。 要测量的通孔在阵列的列中形成。 通过强制通过阵列列和参考列的预定电流来检测通过或接触故障。 通过比较所得的电压降来获得故障分析。

公开(公告)号：US20040225869A1

公开(公告)日：2004-11-11

申请号：US10776024

申请日：2004-02-10

Applicant: STMicroelectronics S.r.I.

Inventor： Andrea Pagni ,  Fabrizio Lucini ,  Danilo Pietro Pau ,  Antonio Maria Borneo ,  Vittorio Zaccaria

IPC: G06F009/44

CPC classification number: G06F9/30174 ,  G06F9/30098 ,  G06F9/30189 ,  G06F9/3879

Abstract: A procedure for translating ARM instructions of a first set into instructions of a second set for execution on an LX processor comprising a core provides a first set of registers corresponding to the ARM instructions and a second set of registers corresponding to the instructions that can be executed on the LX processor. Each register of the first set is mapped in a corresponding register of the second set designed to emulate the behavior of the first register, obtaining a unique independent translation of the first set into the second set. The translation is performed by a translation device external to the LX core without altering the core, and the translation operating without accessing resources of the core, by the translating device intercepting accesses of the core to the storage area reserved to the ARM instructions.

Abstract translation: 用于将第一集合的ARM指令转换为用于在包括核的LX处理器上执行的第二集合的指令的过程提供对应于ARM指令的第一组寄存器和对应于可执行的指令的第二组寄存器 在LX处理器上。 将第一组的每个寄存器映射到第二组的对应寄存器中，该寄存器被设计为模拟第一寄存器的行为，从而获得第一集合到第二集合中的唯一的独立转换。 翻译由LX核心外部的翻译设备执行，而不改变核心，并且通过翻译设备将核心的访问拦截到保留给ARM指令的存储区域，而不会访问核心的资源。

公开(公告)号：US20040213471A1

公开(公告)日：2004-10-28

申请号：US10424141

申请日：2003-04-25

Applicant: STMicroelectronics S.r.I.

Inventor： Mauro De Ponti ,  Marco Ferretti ,  Matteo Boffadossi

IPC: G06K009/36 ,  G06K009/46

CPC classification number: H04N19/93 ,  H04N19/13 ,  H04N19/14 ,  H04N19/42 ,  H04N19/90 ,  H04N19/91

Abstract: A method of compressing a stream of pixel data relative a two-dimensional object, pixels of which are scanned by rows from a source device to a receiver device, includes defining an extended context window to include a pair of pixels following a last encoded pixel on the row being scanned and the respective triplets of neighboring pixels belonging to the preceding row. The method includes defining a first distinct context array of pixels of the extended context window for the pixel of the pair immediately following the last encoded pixel, and a second context array of pixels of the extended context window for the other pixel of the pair. An extended context value relative to each pixel of the pair is calculated, and the extended context value relative to a first pixel immediately following the last encoded pixel is compared with an extended threshold. If the extended context value is less than the extended threshold, then encoding the first and second pixels of the pair, and if the extended context value relative to the first pixel of the pair exceeds the extended threshold, then carrying out simultaneously a parallel processing and encoding of both pixels according to an encoding routine.

Abstract translation: 压缩像素数据相对于二维对象（其像素从源设备被扫描的行）到接收器设备的方法，包括定义扩展上下文窗口以包括在最后编码像素之后的一对像素 正在被扫描的行以及属于前一行的相邻像素的相应三元组。 该方法包括为紧邻在最后编码像素之后的对的像素定义扩展上下文窗口的第一个不同上下文阵列的像素，以及该对的另一个像素的扩展上下文窗口的第二上下文阵列的扩展上下文窗口。 计算相对于该对中的每个像素的扩展上下文值，并将相对于紧接在最后编码像素之后的第一像素的扩展上下文值与扩展阈值进行比较。 如果扩展上下文值小于扩展阈值，则对该对的第一和第二像素进行编码，并且如果相对于该对的第一像素的扩展上下文值超过扩展阈值，则同时执行并行处理和 根据编码程序编码两个像素。

公开(公告)号：US20040208063A1

公开(公告)日：2004-10-21

申请号：US10675221

申请日：2003-09-30

Applicant: STMicroelectronics S.r.I.

Inventor： Rino Micheloni ,  Giovanni Campardo

IPC: G11C011/34 ,  G11C016/04

CPC classification number: G11C29/82 ,  G11C16/04 ,  G11C16/16 ,  G11C29/44 ,  G11C2029/1208

Abstract: The invention relates to a method for erasing non-volatile memory cells, and to a corresponding non-volatile memory device of the programmable and electrically erasable type implementing the method, and comprising a memory cell array organized in a row-and-column layout, and divided in array sectors, including at least one row decode circuit portion being supplied positive and negative voltages. The method is applied whenever the issue of the erase algorithm is negative, and comprises the following steps: forcing an incompletely erased sector into a read condition; scanning the rows of said sector to check for the possible presence of a spurious current indicating a fail state; identifying and electrically isolating the failed row; re-addressing from said failed row to a redundant row provided in the same sector; re-starting the erase algorithm.

Abstract translation: 本发明涉及一种用于擦除非易失性存储单元的方法，以及实现该方法的可编程和电可擦除类型的相应非易失性存储器件，并且包括以行和列布局组织的存储单元阵列， 并且被划分成阵列扇区，包括至少一个行解码电路部分被提供正和负电压。 每当擦除算法的问题为负时，该方法被应用，并且包括以下步骤：强制将未完全擦除的扇区进入读取状态; 扫描所述扇区的行以检查指示故障状态的寄生电流的可能存在; 识别和电隔离失败的行; 从所述故障行重新寻址到在同一扇区中提供的冗余行; 重新启动擦除算法。

公开(公告)号：US20040190336A1

公开(公告)日：2004-09-30

申请号：US10724023

申请日：2003-11-26

Applicant: STMicroelectronics S.r.I

Inventor： Emanuele Confalonieri ,  Antonio Geraci ,  Vincenzo Dima ,  Nicola Del Gatto

IPC: G11C011/34

CPC classification number: G11C16/3459 ,  G11C11/5628 ,  G11C16/3454 ,  G11C2211/5621

Abstract: A method for management of the programming controls in a multilevel device is provided. During the control step cells are not controlled all together but they are conveniently selected in order to reduce the source resistance and consumption effect, but without penalizing change times.

Abstract translation: 提供了一种用于管理多电平设备中的编程控制的方法。 在控制步骤期间，电池不能全部控制，但是它们方便地选择，以便降低电源电阻和消耗效应，但不影响变化时间。

公开(公告)号：US20040183625A1

公开(公告)日：2004-09-23

申请号：US10787819

申请日：2004-02-26

Applicant: STMicroelectronics S.r.I

Inventor： Andrea Baschirotto ,  Piertro Liguori ,  Vittorio Colonna ,  Gabriele Gandolfi

IPC: H03H007/00 ,  H03H011/00

CPC classification number: H03H11/1291 ,  H03H7/24 ,  H03H11/24

Abstract: A control system for the characteristic parameters of an active filter includes: a system for the determination of the technological distribution of the components that provides the information related to said technological distribution of the components; an elaboration system for said information related to said technological distribution of the components; an active filter including at least two programmable passive circuital elements receiving said information related to said technological distribution of the components; said elaboration system, being aware of the topology for said active filter, comprises means for determining the value for said at least two programmable passive circuital elements; means for correcting the value for said at least two programmable passive circuital elements according to the value of the information related to said technological distribution of the components; means for determining the programming values for said at least two programmable passive circuital elements.

Abstract translation: 用于有源滤波器的特征参数的控制系统包括：用于确定提供与组件的所述技术分布有关的信息的组件的技术分布的系统; 用于与所述组件的所述技术分布相关的所述信息的详细系统; 有源滤波器，包括至少两个可编程无源电路元件，其接收与所述组件的所述技术分布有关的所述信息; 所述精细化系统意识到所述有源滤波器的拓扑结构包括用于确定所述至少两个可编程无源电路元件的值的装置; 用于根据与所述组件的所述技术分布相关的信息的值来校正所述至少两个可编程无源电路元件的值的装置; 用于确定所述至少两个可编程无源电路元件的编程值的装置。

公开(公告)号：US20040179622A1

公开(公告)日：2004-09-16

申请号：US10736237

申请日：2003-12-15

Applicant: STMicroelectronics S.r.I.

Inventor： Antonino Calabro ,  Domenico Porto

IPC: H04B014/04

CPC classification number: B82Y10/00 ,  G06N10/00

Abstract: A method for performing a Simon's or Shor's quantum algorithm over a function encoded with n qubits is provided. The method includes performing a superposition operation over a set of input vectors for generating a superposition vector, performing an entanglement operation for generating a corresponding entanglement vector, and performing an interference operation for generating a corresponding output vector. The superposition operation is carried out in a comparably fast manner by generating the superposition vector by identifying the non-null components thereof and by calculating, as a function of the n qubits, the value nulln/2 of all the non-null components of the superposition vector, and by calculating indices of these components according to an arithmetic succession. The seed of this calculation is 1 and the common difference is 2n. The method may be implemented in a quantum gate.

Abstract translation: 提供了一种用n量子位编码的函数执行Simon's或Shor's量子算法的方法。 该方法包括对一组输入矢量执行叠加操作以产生叠加矢量，执行用于产生相应纠缠矢量的纠缠操作，以及执行用于产生相应输出矢量的干涉操作。 通过产生叠加矢量通过识别其非零分量并通过根据n个量子位计算所有非零值的值½来以相当快的方式执行叠加操作 叠加矢量的分量，以及根据算术连续性计算这些分量的指标。 该计算的种子为1，公差为2 。 该方法可以在量子门中实现。

公开(公告)号：US20040154411A1

公开(公告)日：2004-08-12

申请号：US10721766

申请日：2003-11-25

Applicant: STMicroelectronics S.r.I.

Inventor： Marco Viti

IPC: G01L003/02

CPC classification number: H02P6/182

Abstract: A method for detecting the angular position of a rotor in a brushless electric motor, of the type in which the emission of a polarity signal of the back electromotive force by a detection circuitry associated with the motor, includes the using a bi-directional counter for counting the residence time difference of the logic states null0null and null1null at the output of the detection circuitry. The method is aimed at improving the detection of the instantaneous position of the rotor in a brushless motor through the detection of the zero-crossing signal.

Abstract translation: 一种用于检测无刷电动机中的转子的角位置的方法，其中通过与电动机相关联的检测电路发射反电动势的极性信号的类型包括使用双向计数器 计数在检测电路的输出处的逻辑状态“0”和“1”的停留时间差。 该方法旨在通过检测过零信号来改善无刷电动机中转子的瞬时位置的检测。

公开(公告)号：US20040129989A1

公开(公告)日：2004-07-08

申请号：US10650452

申请日：2003-08-27

Applicant: STMicroelectronics S.r.I. ,  Nokia Corporation

Inventor： Sarah Zerbini ,  Angelo Merassi ,  Guido Spinola Durante ,  Biagio De Masi

IPC: G01L001/06 ,  G01P015/03 ,  H01L023/00 ,  H04Q007/34 ,  G01B005/30

CPC classification number: G01P1/127 ,  G01P15/06 ,  G01P15/0802 ,  G01P15/0891 ,  G01P15/18 ,  G01P2015/0814 ,  H01H1/0036 ,  H01H35/146

Abstract: An inertial sensor with failure threshold includes a first body and a second body, which can move relative to one another and are constrained by a plurality of elastic elements, and a sample element connected between the first body and the second body and shaped so as to be subjected to a stress when the second body is outside of a relative resting position with respect to the first body. The sample element has at least one weakened region. The sensor may also include additional sample elements connected between the first and second bodies.

Abstract translation: 具有故障阈值的惯性传感器包括第一主体和第二主体，其可以相对于彼此移动并被多个弹性元件约束;以及样本元件，其连接在第一主体和第二主体之间，并且成形为 当第二主体相对于第一主体位于相对静止位置之外时受到应力。 样品元件具有至少一个弱化区域。 传感器还可以包括连接在第一和第二主体之间的附加样本元件。