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公开(公告)号：US20180026058A1
公开(公告)日：2018-01-25
申请号：US15709791
申请日：2017-09-20
Applicant: STMicroelectronics (Grenoble 2) SAS , STMicroelectronics (Research & Development) Limited
Inventor： Pascal Mellot , Stuart McLeod , Bruce Rae , Marc Drader
IPC: H01L27/144 , H01L31/0216 , H01L27/148 , G01S7/497 , H01L27/146 , H01L31/107 , G01S7/486
CPC classification number: H01L27/1443 , G01S7/4863 , G01S7/4865 , G01S7/497 , H01L27/1446 , H01L27/14623 , H01L27/14818 , H01L31/02164 , H01L31/107
Abstract: A circuit may include an array of single photon avalanche diode (SPAD) cells, each SPAD cell configured to be selectively enabled by an activation signal. The circuit may include a control circuit configured to selectively enable a subset of the array of SPAD cells based on a measured count rate of the array of SPAD cells.
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公开(公告)号：US20170337896A1
公开(公告)日：2017-11-23
申请号：US15659449
申请日：2017-07-25
Applicant: STMicroelectronics (Grenoble 2) SAS
Inventor： Marina Nicolas
CPC classification number: G09G5/005 , G06T3/0012 , G06T3/40 , G09G2340/0442
Abstract: A source image is transformed into a destination image having a target aspect ratio. A reference region in the source image is defined. An extended region of interest of the source image having the target aspect ratio and containing the reference region is defined. A set of candidate image regions of increasing resolutions from the extended region of interest is determined, each having the target aspect ratio and containing the reference region. Candidate image regions are scaled to form a candidate target images. A quality metric is used to select a target image providing the best quality metric value.
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公开(公告)号：US09804616B2
公开(公告)日：2017-10-31
申请号：US14616413
申请日：2015-02-06
Applicant: STMicroelectronics (Grenoble 2) SAS
Inventor： Vratislav Michal
Abstract: A switched-mode power supply device includes a power switch configured to transfer power from a supply line to a load in switched-mode; a first oscillator configured to operate at a frequency proportional to a voltage of the supply line; a second oscillator configured to operate at a frequency proportional to a voltage of the load; and a regulator configured to operate the power switch according to a duty cycle based on a ratio between the first and second oscillator frequencies.
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公开(公告)号：US20170287150A1
公开(公告)日：2017-10-05
申请号：US15089134
申请日：2016-04-01
Applicant: STMicroelectronics (Grenoble 2) SAS
Inventor： Mathieu Thivin , Pierre-Francois Pugibet
CPC classification number: G06T7/90 , G06T3/4015 , G06T5/002 , G06T7/408 , G06T2207/10024 , H04N1/60
Abstract: Digital image processing circuitry converts a macro-pixel of an image in a color filter array (CFA) color space to a macro-pixel in a luminance-chrominance (YUV) color space. Chrominance filtering is applied to chrominance components of the converted macro-pixel in the YUV color space, generating a filtered macro-pixel in the YUV color space. The filtered macro-pixel in the YUV color space is converted into a filtered macro-pixel in the CFA color space.
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公开(公告)号：US20170287149A1
公开(公告)日：2017-10-05
申请号：US15088934
申请日：2016-04-01
Applicant: STMicroelectronics (Grenoble 2) SAS
Inventor： Mathieu Thivin , Grégory Roffet
Abstract: Tone mapping is performed by digital image processing circuitry on a macro-pixel basis. A luminance value of a macro-pixel of a digital image in a color space is determined. The macro-pixel includes a plurality of individual pixels. Respective tone-mapping gain values of each pixel of the macro-pixel are determined based on the determined luminance value of the macro-pixel. The determined tone-mapping gains are applied to the respective pixels of the macro-pixel. The color space may be a CFA color space, such as a Bayer color space.
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Patent Agency Ranking
公开(公告)号：US09781404B2
公开(公告)日：2017-10-03
申请号：US14953938
申请日：2015-11-30
Applicant: STMICROELECTRONICS (GRENOBLE 2) SAS
Inventor： Frankie Eymard , Jean-Louis Labyre
CPC classification number: H04N13/194 , H04N7/24 , H04N13/10 , H04N13/106 , H04N13/161 , H04N19/16 , H04N2013/0088
Abstract: The present disclosure relates to a method for transmitting two consecutive pairs of images. The method may include decimating each image with a ratio of 2, assembling the two decimated images of each pair in a composite image, transmitting the composite images, and reconstructing complete images from the composite images. In decimation, the information removed from the images of the first pair may be kept in the images of the second pair, from the spatial point of view, and the complete images may be reconstructed by de-interlacing processing from the composite images.
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357.发明授权公开(公告)号：US09773740B2
公开(公告)日：2017-09-26
申请号：US14821902
申请日：2015-08-10
Applicant: STMicroelectronics (Grenoble 2) SAS
Inventor： Karine Saxod , Marika Sorrieul
IPC: H01L23/00 , H01L27/146 , H01L23/31 , H01L21/56
CPC classification number: H01L23/562 , H01L21/56 , H01L23/3121 , H01L23/315 , H01L23/3171 , H01L24/17 , H01L24/29 , H01L24/30 , H01L24/32 , H01L24/48 , H01L24/73 , H01L24/81 , H01L24/97 , H01L27/14618 , H01L27/14683 , H01L31/02005 , H01L31/0203 , H01L31/1876 , H01L2224/1329 , H01L2224/13291 , H01L2224/14179 , H01L2224/2929 , H01L2224/29291 , H01L2224/30135 , H01L2224/32225 , H01L2224/48227 , H01L2224/73203 , H01L2224/81862 , H01L2224/81874 , H01L2924/00014 , H01L2924/15311 , H01L2924/16235 , H01L2924/181 , H01L2924/00012 , H01L2224/45099
Abstract: A method for fabricating an electronic device, and an electronic device in a stacked configuration, includes a rear face of an integrated-circuit chip that is fixed to a front face of a support wafer. A protective wafer is located facing and at a distance from the front face of the chip, and an infused adhesive is interposed between the chip and the protective wafer and located on a zone of the front face of the chip outside a central region of this front face. The infused adhesive includes a curable adhesive and solid spacer elements infused in the curable adhesive. An obstruction barrier is arranged between the chip and the protective wafer and is disposed outside the central region of the front face of the chip. An encapsulation ring surrounds the chip, the protective wafer and the obstruction barrier.
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公开(公告)号：US09754853B2
公开(公告)日：2017-09-05
申请号：US15050216
申请日：2016-02-22
Inventor： David Auchere , Laurent Marechal , Laurent Schwarz , Yvon Imbs
IPC: H01L23/48 , H01L23/31 , H01L23/64 , H01L23/66 , H01L23/00 , H01Q1/22 , H01L21/48 , H01L21/52 , H01L21/56 , H01L23/13 , H01L23/498
CPC classification number: H01Q1/38 , H01L21/4853 , H01L21/486 , H01L21/4889 , H01L21/52 , H01L21/56 , H01L23/13 , H01L23/3114 , H01L23/3128 , H01L23/315 , H01L23/481 , H01L23/498 , H01L23/49811 , H01L23/49827 , H01L23/645 , H01L23/66 , H01L24/81 , H01L2223/6677 , H01L2224/16227 , H01L2924/15311 , H01L2924/1815 , H01Q1/2283
Abstract: An electronic device includes a support board having a mounting face and an integrated circuit chip mounted on the mounting face. An encapsulation block embeds the integrated circuit chip, the encapsulation block extending above the integrated circuit chip and around the integrated circuit chip on the mounting face of the support board. The encapsulation block includes a front face with a hole passing through the encapsulation block to uncovering at least part of an electrical contact. A layer made of an electrically conducting material fills the hole to make electrical connection to the electrical contact and further extends over the front face of the encapsulation block.
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公开(公告)号：US09747863B2
公开(公告)日：2017-08-29
申请号：US14607523
申请日：2015-01-28
Applicant: STMicroelectronics (Grenoble 2) SAS
Inventor： Marina Nicolas
CPC classification number: G09G5/005 , G06T3/0012 , G06T3/40 , G09G2340/0442
Abstract: A source image is transformed into a destination image having a target aspect ratio. A reference region in the source image is defined. An extended region of interest of the source image having the target aspect ratio and containing the reference region is defined. A set of candidate image regions of increasing resolutions from the extended region of interest is determined, each having the target aspect ratio and containing the reference region. Candidate image regions are scaled to form a candidate target images. A quality metric is used to select a target image providing the best quality metric value.
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公开(公告)号：US09728578B2
公开(公告)日：2017-08-08
申请号：US14454776
申请日：2014-08-08
Applicant: STMicroelectronics (Grenoble 2) SAS , STMicroelectronics (Research & Development) Limited
Inventor： Graeme Storm , Christophe Mandier , Laurence Stark
IPC: H01L27/148 , H04N5/355 , H04N5/359 , H04N5/3745 , H01L27/146
CPC classification number: H01L27/14812 , H01L27/14609 , H01L27/14638 , H01L27/14643 , H04N5/355 , H04N5/3559 , H04N5/3597 , H04N5/37452
Abstract: A pixel arrangement includes a photodiode, a reset transistor configured to be controlled by a reset signal and coupled to a reset input voltage, a transfer gate transistor configured to transfer charge from the photodiode to a node, wherein the transfer gate transistor is controlled by a transfer gate voltage, and a source follower transistor controlled by the voltage on the node and coupled to a source follower voltage. A capacitor is coupled between the node and an input voltage. During a read operation the input voltage is increased to boost the voltage at the node. The increased input voltage may, for example, be one the reset input voltage, said source follower voltage, said transfer gate voltage and a boosting voltage.
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