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公开(公告)号：US20180083006A1
公开(公告)日：2018-03-22
申请号：US15706952
申请日：2017-09-18
Applicant: Commissariat A L'Energie Atomique et aux Energies Alternatives , STMicroelectronics (CROLLES 2) SAS
Inventor： Francois ANDRIEU , Remy BERTHELON
IPC: H01L27/092 , H01L27/12 , H01L29/423 , H01L29/78
CPC classification number: H01L27/0922 , H01L21/823807 , H01L27/0207 , H01L27/092 , H01L27/1203 , H01L29/1054 , H01L29/4238 , H01L29/7848
Abstract: An integrated circuit is provided, including: a first pair including a first nMOS transistor and a first pMOS transistor; a second pair including a second nMOS transistor and a second pMOS transistor; the first and the second nMOS transistors including a channel region made of silicon that is subjected to tensile stress, and their respective gates being positioned at least 250 nm from a border of their active zone; and a third pair including a third nMOS transistor having a same construction as the second nMOS transistor and a third pMOS transistor having a same construction as the first pMOS transistor and having a tensile stress that is lower by at least 250 MPa than the tensile stress of the channel region, respective gates of the transistors of the third pair being positioned at most 200 nm from a border of their active zone.
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公开(公告)号：US20180083005A1
公开(公告)日：2018-03-22
申请号：US15706935
申请日：2017-09-18
Applicant: Commissariat A L'Energie Atomique et aux Energies Alternatives , STMICROELECTRONICS (CROLLES 2) SAS
Inventor： Francois ANDRIEU , Remy BERTHELON
IPC: H01L27/092 , H01L29/78 , H01L29/161 , H01L29/167
CPC classification number: H01L27/0922 , H01L21/823807 , H01L27/0207 , H01L27/092 , H01L29/1054 , H01L29/161 , H01L29/167 , H01L29/7842
Abstract: An integrated circuit is provided, including a first pair including a first nMOS transistor and a first pMOS transistor; a second pair including a second nMOS transistor and a second pMOS transistor; the first and second pMOS transistors including a channel that is subjected to compressive stress and made of an SiGe alloy, and a gate of said transistors being positioned at least 250 nm from a border of an active zone of said transistors; a third pair including a third nMOS transistor having a same construction as the first nMOS transistor and a third pMOS transistor having a same construction as the second pMOS transistor and exhibiting a compressive stress that is lower by at least 250 MPa, the gate of said transistors of the third pair being positioned at most 200 nm from the border.
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公开(公告)号：US09923016B2
公开(公告)日：2018-03-20
申请号：US15160811
申请日：2016-05-20
Applicant: STMicroelectronics (Crolles 2) SAS
Inventor： Frédéric Lalanne , Pierre Emmanuel Marie Malinge
IPC: H01L27/146 , H04N5/3745 , H04N5/355
CPC classification number: H01L27/14656 , H01L27/146 , H01L27/14603 , H01L27/14609 , H01L27/1463 , H01L27/14636 , H04N5/3559 , H04N5/3745 , H04N5/37452
Abstract: A pixel including a photodiode having a first pole coupled through a transfer MOS transistor to a node for sensing charges of a first type stored in the photodiode, and having a second pole connected to a storage capacitor and to a circuit for reading charges of a second type sent to the storage capacitor.
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公开(公告)号：US09917124B2
公开(公告)日：2018-03-13
申请号：US14919836
申请日：2015-10-22
Applicant: Commissariat à l'Energie Atomique et aux Energies Alternatives , STMicroelectronics (Crolles 2) SAS , STMicroelectronics (GRENOBLE 2) SAS
Inventor： Yvon Cazaux , François Roy , Arnaud Laflaquiere , Marie Guillon
IPC: H01L27/146 , H01L27/148 , H01L27/12
CPC classification number: H01L27/14636 , H01L27/1203 , H01L27/14605 , H01L27/14614 , H01L27/1463
Abstract: An image sensor arranged inside and on top of a semi-conductor substrate having a front surface and a rear surface, the sensor including a plurality of pixels, each including: a photosensitive area, a reading area, and a storage area extending between the photosensitive area and the reading area; a vertical insulated electrode including an opening of transfer between the photosensitive area and the storage area; and at least one insulation element among the following: a) a layer of an insulating material extending under the surface of the photosensitive area and of the storage area and having its front surface in contact with the rear surface of the electrode; and b) an insulating wall extending vertically in the opening, or under the opening.
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公开(公告)号：US20180048123A1
公开(公告)日：2018-02-15
申请号：US15555639
申请日：2015-03-06
Applicant: STMicroelectronics (Crolles 2) SAS , Centre National de la Recherche Scientifique , Universite Paris SUD
Inventor： Mathias Prost , Moustafa El Kurdi , Philippe Boucaud , Frederic Boeuf
Abstract: A germanium waveguide is formed from a P-type silicon substrate that is coated with a heavily-doped N-type germanium layer and a first N-type doped silicon layer. Trenches are etched into the silicon substrate to form a stack of a substrate strip, a germanium strip, and a first silicon strip. This structure is then coated with a silicon nitride layer.
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Patent Agency Ranking
公开(公告)号：US20180047770A1
公开(公告)日：2018-02-15
申请号：US15790432
申请日：2017-10-23
Applicant: STMicroelectronics (Crolles 2) SAS
Inventor： François Roy , Helene Wehbe-Alause , Olivier Noblanc
IPC: H01L27/146 , H01L27/12
CPC classification number: H01L27/14612 , H01L27/1203 , H01L27/1463 , H01L27/1464 , H01L27/14643 , H01L27/14645 , H01L27/14687 , H01L27/14689
Abstract: A back-side illuminated pixel including a semiconductor substrate of a first conductivity type coated, on the front side of the pixel, with a three-layer assembly successively including a first layer of the second conductivity type, an insulating layer, and a second semiconductor layer. The three-layer assembly is interrupted in a central portion of the pixel by a transfer region of the first conductivity type laterally delimited by an insulated conductive wall extending from the front surface, Transistors are formed in the second semiconductor layer.
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公开(公告)号：US20180025945A1
公开(公告)日：2018-01-25
申请号：US15450114
申请日：2017-03-06
Applicant: STMicroelectronics (Crolles 2) SAS
Inventor： Pascal Chevalier , Gregory Avenier
IPC: H01L21/8228 , H01L21/265 , H01L29/06 , H01L21/285 , H01L21/311 , H01L27/102 , H01L21/761 , H01L21/02
CPC classification number: H01L21/82285 , H01L21/02532 , H01L21/02639 , H01L21/26513 , H01L21/28518 , H01L21/31111 , H01L21/761 , H01L27/0623 , H01L27/0716 , H01L27/1022 , H01L29/0646 , H01L29/0649 , H01L29/0804 , H01L29/0821 , H01L29/42304 , H01L29/66272 , H01L29/732
Abstract: A PNP transistor is manufactured in parallel with the manufacture of NPN, NMOS, and PMOS transistors. A first semiconductor layer is deposited on a P-type doped semiconductor substrate and divided into first, second, and third regions, with the third region forming the base. An insulating well is deeply implanted into the substrate. First and second third wells, respectively of N-type and P-type are formed to extend between the second region and third region and the insulating well. A third well of P-type is formed below the third region to provide the collector. Insulating layers are deposited over the third region and patterned to form an opening. Epitaxial growth of a second P-type doped semiconductor layer is performed in the opening to provide the emitter.
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公开(公告)号：US09876076B2
公开(公告)日：2018-01-23
申请号：US14956594
申请日：2015-12-02
Applicant: STMICROELECTRONICS (CROLLES 2) SAS
Inventor： Emmanuel Perrin
IPC: H01L29/06 , H01L29/66 , H01L21/84 , H01L27/12 , H01L21/8238 , H01L21/762
CPC classification number: H01L29/0649 , H01L21/762 , H01L21/76229 , H01L21/76283 , H01L21/823878 , H01L21/84 , H01L27/1203 , H01L29/665 , H01L29/66545 , H01L29/6656 , H01L29/66628
Abstract: An integrated circuit may include an SOI substrate having a buried insulating layer, and a semiconductor film above the buried insulating layer. The semiconductor film may have first patterns in a first zone defining gate regions of first MOS transistors and also first dummy gate regions. The first zone may include two domains having a space therebetween, and the space may be filled by at least one insulating material and be situated between two dummy gate regions above a region of the supporting substrate without any insulating trench.
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公开(公告)号：US20180012935A1
公开(公告)日：2018-01-11
申请号：US15694463
申请日：2017-09-01
Inventor： Philippe Boivin , Simon Jeannot
CPC classification number: H01L27/2436 , G11C13/0004 , G11C2213/79 , G11C2213/82 , H01L27/2463 , H01L45/04 , H01L45/085 , H01L45/1226 , H01L45/146 , H01L45/147 , H01L45/1666
Abstract: The disclosure relates to a memory cell formed in a wafer comprising a semiconductor substrate covered with a first insulating layer, the insulating layer being covered with an active layer made of a semiconductor, the memory cell comprising a selection transistor having a control gate and a first conduction terminal connected to a variable-resistance element, the gate being formed on the active layer and having a lateral flank covered with a second insulating layer, the variable-resistance element being formed by a layer of variable-resistance material, deposited on a lateral flank of the active layer in a first trench formed through the active layer along the lateral flank of the gate, a trench conductor being formed in the first trench against a lateral flank of the layer of variable-resistance material.
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公开(公告)号：US20180003895A1
公开(公告)日：2018-01-04
申请号：US15367901
申请日：2016-12-02
Applicant: STMicroelectronics (Crolles 2) SAS
Inventor： Charles Baudot
CPC classification number: G02B6/125 , G02B6/1228 , G02B6/136 , G02B2006/12061 , G02B2006/12097 , G02B2006/121 , G02B2006/12173 , G02B2006/12176
Abstract: A photonic integrated device includes a first waveguide and a second waveguide. The first and second waveguides are mutually coupled at a junction region the includes a bulge region.
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