公开(公告)号：US20150268133A1

公开(公告)日：2015-09-24

申请号：US14218482

申请日：2014-03-18

Applicant: STMicroelectronics S.r.l. ,  STMicroelectronics International N.V.

Inventor： Om Ranjan ,  Giampiero Borgonovo ,  Deepak Baranwal

IPC: G01M99/00

CPC classification number: G06F11/0736 ,  G05B19/0428 ,  G05B23/0254 ,  G05B2219/2637 ,  G06F11/2205 ,  G06F11/3013

Abstract: A safety system monitors faults in an embedded control system. The embedded control system is modeled to produce one or more model check values by calculating how many clock cycles will pass between an initialization time point and at least one event time point for a specific event. The initialization time point is a certain point in an initialization function of a scheduler in the embedded control system. The at least one event time point is an expected number of clock cycles to pass before a specific event occurs. In operation, the embedded control system is initialized, a current clock cycle counter value is retrieved at a certain point in the initialization, and either an occurrence or an absence of an occurrence of a scheduled event is recognized. A current clock cycle value is recorded upon the recognition, and a mathematic check value is produced from the clock cycle value stored at the certain point in the initialization and the clock cycle value recorded upon the recognition. Subsequently, the model check value is compared to the mathematic check value, and action is taken based on the comparison.

Abstract translation: 安全系统监控嵌入式控制系统中的故障。 嵌入式控制系统被建模为通过计算在特定事件的初始化时间点和至少一个事件时间点之间经过多少个时钟周期来产生一个或多个模型检查值。 初始化时间点是嵌入式控制系统中的调度器的初始化功能中的某一点。 至少一个事件时间点是在特定事件发生之前要通过的期望数量的时钟周期。 在操作中，初始化嵌入式控制系统，在初始化中的某一点检索当前的时钟周期计数器值，并且识别调度事件的发生或不存在。 在识别时记录当前时钟周期值，并且从存储在初始化中的某一点的时钟周期值和在识别时记录的时钟周期值产生数学校验值。 随后，将模型检查值与数学检查值进行比较，并根据比较进行动作。

公开(公告)号：US20150263707A1

公开(公告)日：2015-09-17

申请号：US14216719

申请日：2014-03-17

Applicant: STMicroelectronics International N.V.

Inventor： Ravinder KUMAR

IPC: H03K3/3565

CPC classification number: H03K3/3565

Abstract: A Schmitt Trigger is implemented in FDSOI technology. The Schmitt Trigger includes a first inverting stage having an NMOS and PMOS transistor having their drains tied together. The NMOS and PMOS transistor each have a first gate coupled to the input voltage and a back gate coupled to the output of the Schmitt Trigger.

Abstract translation: 施密特触发器采用FDSOI技术实现。 施密特触发器包括具有连接在一起的NMOS和PMOS晶体管的第一反相级。 NMOS和PMOS晶体管各自具有耦合到输入电压的第一栅极和耦合到施密特触发器的输出的后栅极。

公开(公告)号：US20150179282A1

公开(公告)日：2015-06-25

申请号：US14640601

申请日：2015-03-06

Applicant: STMicroelectronics International N.V.

Inventor： Nishu Kohli

IPC: G11C29/10

CPC classification number: G11C29/10 ,  G01R31/318307 ,  G01R31/318342 ,  G01R31/318371 ,  G11C11/2273 ,  G11C11/2275 ,  G11C11/34 ,  G11C11/4063 ,  G11C29/00 ,  G11C29/14 ,  G11C29/24 ,  G11C29/50 ,  G11C29/52 ,  G11C29/54 ,  G11C29/56004 ,  G11C29/56008

Abstract: An embodiment of a method for automated test pattern generation (ATPG), a system for ATPG, and a memory configured for ATPG. For example, an embodiment of a memory includes a first test memory cell, a data-storage memory cell, and a test circuit configured to enable the test cell and to disable the data-storage cell during a test mode.

Abstract translation: 用于自动测试模式生成（ATPG）的方法，用于ATPG的系统和为ATPG配置的存储器的实施例。 例如，存储器的实施例包括第一测试存储器单元，数据存储存储器单元和被配置为使能测试单元并且在测试模式期间禁用数据存储单元的测试电路。

公开(公告)号：US09054637B1

公开(公告)日：2015-06-09

申请号：US14152523

申请日：2014-01-10

Applicant: STMicroelectronics International N.V.

Inventor： Gauri Mittal ,  Kallol Chatterjee

IPC: H03B5/36 ,  H03B5/04 ,  H03B5/06

CPC classification number: H03B5/364 ,  H03B5/04 ,  H03B5/06 ,  H03B2200/0012 ,  H03B2200/0038 ,  H03B2200/0066 ,  H03B2200/0094

Abstract: An amplitude limiting circuit for a crystal oscillator circuit includes a current source configured to supply drive current to the crystal oscillator circuit and a current sensing circuit configured to sense operating current in an inverting transistor of the crystal oscillator circuit. The current comparison circuit functions to compare the sensed operating current to at least a reference current and generate an output signal. A current control circuit generates a control signal for controlling operation of the current source in response to the output signal.

Abstract translation: 晶体振荡器电路的振幅限制电路包括被配置为向晶体振荡器电路提供驱动电流的电流源和被配置为感测晶体振荡器电路的反相晶体管中的工作电流的电流感测电路。 当前比较电路用于将感测的工作电流与至少参考电流进行比较，并产生输出信号。 电流控制电路响应于输出信号产生用于控制电流源的操作的控制信号。

公开(公告)号：US20150145608A1

公开(公告)日：2015-05-28

申请号：US14090759

申请日：2013-11-26

Applicant: STMicroelectronics International N.V.

Inventor： Amit Katyal

IPC: H03K3/03

CPC classification number: H03K3/0315 ,  G05F3/262 ,  H03L7/0995

Abstract: A phase locked loop includes a voltage-controlled oscillator and a current mirror circuit that supplies a drive current to the voltage-controlled oscillator. The current mirror circuit includes a filter between a bias current generator and current mirror transistor. The filter includes a first and a second switch driven in unison with a small duty cycle.

Abstract translation: 锁相环包括压控振荡器和向压控振荡器提供驱动电流的电流镜电路。 电流镜电路包括偏置电流发生器和电流镜晶体管之间的滤波器。 该滤波器包括以小占空比同时驱动的第一和第二开关。

公开(公告)号：US20150130531A1

公开(公告)日：2015-05-14

申请号：US14079512

申请日：2013-11-13

Applicant: STMicroelectronics International N.V.

Inventor： Aswani Aditya Kumar TADINADA ,  Tanmoy SEN

IPC: G05F5/00

CPC classification number: G05F5/00 ,  G01K1/026 ,  G01K7/01

Abstract: An integrated circuit die includes multiple temperature sensor units each for measuring the temperature of respective regions of a semiconductor substrate of the integrated circuit die. The temperature sensor units are each coupled to a multiplexer by respective groups of signal lines. The signal lines include resistance compensation areas for maintaining a particular ratio of resistances of the signal lines of each group.

Abstract translation: 集成电路管芯包括多个温度传感器单元，每个温度传感器单元用于测量集成电路管芯的半导体衬底的相应区域的温度。 温度传感器单元各自通过相应的信号线组耦合到多路复用器。 信号线包括用于维持每组信号线的电阻的特定比率的电阻补偿区域。

公开(公告)号：US09018987B1

公开(公告)日：2015-04-28

申请号：US14090744

申请日：2013-11-26

Applicant: STMicroelectronics International N.V.

Inventor： Abhirup Lahiri

IPC: H03B19/00 ,  H03L7/00 ,  H03K3/03 ,  H03K23/54 ,  H03L7/099

CPC classification number: H03L7/0995 ,  H03K3/0315 ,  H03K23/54 ,  H03L7/24

Abstract: A phase locked loop includes a voltage controlled oscillator and a frequency divider or frequency multiplier. The voltage controlled oscillator and the frequency divider/multiplier are coupled together in a stacked configuration. A drive current is supplied to the voltage controlled oscillator. The drive current passes from the voltage controlled oscillator to the frequency divider/multiplier, thereby driving the frequency divider/multiplier with the same drive current that was supplied to the voltage controlled oscillator.

Abstract translation: 锁相环包括压控振荡器和分频器或倍频器。 压控振荡器和分频器/乘法器以堆叠配置耦合在一起。 驱动电流被提供给压控振荡器。 驱动电流从压控振荡器传递到分频器/乘法器，从而以提供给压控振荡器的相同驱动电流来驱动分频器/乘法器。

公开(公告)号：US20150110123A1

公开(公告)日：2015-04-23

申请号：US14059412

申请日：2013-10-21

Applicant: STMICROELECTRONICS INTERNATIONAL N.V.

Inventor： Pierre Muller ,  Samuel Dubouloz

IPC: H04L12/863

CPC classification number: H04L47/6245 ,  H04L47/28 ,  H04L49/901

Abstract: A plurality of frames of data are transmitted over a serial interface in a manner that limits interference on the interface. This involves generating a pseudo-random number and asserting a read control signal at a moment in time, wherein a timing of the moment in time is influenced by the pseudo-random number. In response to the asserted read control signal, a frame of data is read from a data buffer. The read frame of data is then transmitted over the serial interface. A number of alternative embodiments are possible, such as embodiments in which buffer read operations are triggered based on the buffer fill level, and other embodiments in which buffer read operations are triggered by a timer. By using the pseudo-random number to influence the buffer read operations, timing coherency between the reading of frames is made low, thereby limiting interference.

Abstract translation: 通过串行接口以限制对接口的干扰的方式发送多个数据帧。 这涉及在时刻产生伪随机数并断言读控制信号，其中时刻的定时受到伪随机数的影响。 响应于断言的读取控制信号，从数据缓冲器读取一帧数据。 然后通过串行接口传输读取的数据帧。 一些替代实施例是可能的，例如基于缓冲器填充级别触发缓冲器读取操作的实施例，以及其中缓冲器读取操作由定时器触发的其他实施例。 通过使用伪随机数来影响缓冲器读取操作，使得读取帧之间的定时一致性变低，从而限制干扰。

公开(公告)号：US09015539B2

公开(公告)日：2015-04-21

申请号：US13969259

申请日：2013-08-16

Applicant: STMicroelectronics International N.V.

Inventor： Suraj Prakash

IPC: G11C29/00 ,  G11C29/10 ,  G11C29/50 ,  G11C17/00 ,  G11C29/04

CPC classification number: G11C29/10 ,  G11C17/00 ,  G11C29/50 ,  G11C2029/0401

Abstract: A method for identifying non stuck-at faults in a read-only memory (ROM) includes generating a golden value of a victim cell, providing a fault-specific pattern through an aggressor cell, generating a test reading of the victim cell in response to the provided fault-specific pattern, and determining whether the ROM has at least one non stuck-at fault. The determination is based on a comparison of the golden value and the test reading of the victim cell.

Abstract translation: 用于识别只读存储器（ROM）中的非卡住故障的方法包括生成受害单元的金值，通过侵略者单元提供故障特定模式，响应于 提供的故障特定模式，以及确定ROM是否具有至少一个非卡住故障。 确定是基于对受害者细胞的黄金值和测试读数的比较。

公开(公告)号：US09000963B2

公开(公告)日：2015-04-07

申请号：US14293119

申请日：2014-06-02

Applicant: STMicroelectronics SA ,  STMicroelectronics International N.V.

Inventor： Pratap Narayan Singh ,  Stéphane Le Tual

IPC: H03M1/00 ,  H03K17/22 ,  H03M1/12 ,  H03K17/14 ,  H03K17/687

CPC classification number: H03K17/223 ,  H03K17/145 ,  H03K17/687 ,  H03K2217/0018 ,  H03M1/12

Abstract: The invention concerns a circuit comprising: a first transistor (102) having first and second main current nodes, and a gate node adapted to receive a first timing signal (CLK) for causing the first transistor to transition between conducting and non-conducting states; a biasing circuit (108) coupled to a further node of said first transistor; and a control circuit (110) adapted to control said biasing circuit to apply a first control voltage (VCTRL) to said further node to adjust the timing of at least one of said transitions.

Abstract translation: 本发明涉及一种电路，包括：具有第一和第二主电流节点的第一晶体管（102）和适于接收用于使第一晶体管在导通状态与非导通状态之间转变的第一定时信号（CLK）的栅极节点; 偏置电路（108），耦合到所述第一晶体管的另一节点; 以及适于控制所述偏置电路以对所述另一节点施加第一控制电压（VCTRL）以调整至少一个所述转换的定时的控制电路（110）。