公开(公告)号：US12248662B2

公开(公告)日：2025-03-11

申请号：US18486716

申请日：2023-10-13

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Dong-Goo Kang ,  Yun-kyung Kim ,  Yong-yeon Lee ,  Ji-yeon Kwak ,  Yeo-jun Yoon

IPC: G06F3/041 ,  G06F1/16 ,  G06F3/04817 ,  G06F3/0482 ,  G06F3/04842 ,  G06F3/04847 ,  G06F3/0487 ,  G06F3/0488 ,  G06F3/04883 ,  G06F3/04886 ,  G06F9/451 ,  G11B27/34 ,  H04M1/02 ,  H04M1/72403 ,  H04M1/72469

Abstract: A user terminal device and a displaying method thereof are provided. The user terminal device includes a display configured to display a first screen on a display which is divided by a folding line into a first area and a second area, the second area being larger than the first area with reference to a folding line and including an exposure area that is exposed while the display is folded along the folding line such that the first area faces the second area, a detector configured to detect, while the first screen is displayed, a first folding interaction of folding the display such that the first area faces the second area and a second folding interaction of folding the display such that a first cover corresponding to the first area faces a second cover corresponding to the second area, and a controller configured to, in response to detecting the first folding interaction, display a second screen related to the first screen on the exposure area, and in response to the second folding interaction being detected, display a third screen related to the first screen on the first area or the second area.

公开(公告)号：US12248355B2

公开(公告)日：2025-03-11

申请号：US18194782

申请日：2023-04-03

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hee Dong Shin

IPC: G06F1/32 ,  G06F1/3287 ,  G06F9/44 ,  G06F9/4401 ,  G06F9/445 ,  G06F13/24 ,  G11C7/10 ,  G11C11/406

Abstract: A system on chip (SoC) includes an internal read-only memory (ROM) configured to store a first boot loader; a first internal static random access memory (SRAM) configured to receive a second boot loader output from a booting device, store the second boot loader, and perform a booting sequence according to control of the first boot loader; a second internal SRAM configured to receive a third boot loader output from the booting device, store the third boot loader, and perform a wake-up sequence according to control of the first boot loader; and a dynamic random access memory (DRAM) controller configured to load an operating system (OS) from the booting device into a DRAM according to control of the second boot loader.

公开(公告)号：US12248217B2

公开(公告)日：2025-03-11

申请号：US18540999

申请日：2023-12-15

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Kyungsoo Park ,  Sungyeol Kim ,  Chunsoon Park ,  Kyehoon Lee

IPC: G02F1/1335 ,  H01L25/075 ,  H01L33/10 ,  H01L33/50 ,  H01L33/56

Abstract: According to the disclosure, a display apparatus includes a printed circuit board (PCB), a light emitting diode (LED) chip mounted on the PCB and configured to emit light, an optical dome formed to enclose the LED chip by being dispensed on the LED chip, and a liquid crystal panel configured to block or pass light output from the LED chip, wherein the optical dome may be formed to satisfy 1.70

公开(公告)号：US12248018B2

公开(公告)日：2025-03-11

申请号：US18047366

申请日：2022-10-18

Applicant: Samsung Electronics Co., Ltd.

Inventor： Yeon Ho Jung ,  Jong Wook Kye ,  Min Woo Kwak ,  Mi Joung Kim ,  Chan Wook Park ,  Do Hoon Byun ,  Kwan Seong Lee ,  Jae Ho Lee ,  Jae Seung Choi ,  Hwang Ho Choi

IPC: G01R31/28 ,  G01R31/30 ,  H03K3/011 ,  H03K3/03

Abstract: A semiconductor chip includes a semiconductor device connected between a first node to which a power supply voltage is applied and a second node to which a ground voltage is applied, a first ring oscillator connected to the first node through a first supply switch and the second node through a first ground switch and a second ring oscillator connected to the first node through a second supply switch and the second node through a second ground switch, wherein the first supply and ground switches are configured to operate in response to a first control signal, thereby operating the first ring oscillator, and the second supply and ground switches are configured to operate in response to a second control signal, thereby operating the second ring oscillator.

公开(公告)号：US20250081858A1

公开(公告)日：2025-03-06

申请号：US18602554

申请日：2024-03-12

Applicant: Samsung Electronics Co., Ltd.

Inventor： Dae Yun KIM ,  Hyeok Shin KWON ,  In Su JEON

IPC: H10N60/12

Abstract: A superconducting device includes a frequency-tunable device including a first conductive pad and a second conductive pad which are connected to each other by a Josephson junction, a ferromagnet having a magnetic domain wall, and a control circuit configured to apply a current to the ferromagnet to adjust a position of the magnetic domain wall of the ferromagnet, and to control a resonance frequency of the frequency-tunable device.

公开(公告)号：US20250081654A1

公开(公告)日：2025-03-06

申请号：US18458991

申请日：2023-08-30

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： IKJUN CHOI

IPC: H01L27/146 ,  H01L23/48 ,  H01L23/522 ,  H01L23/528

Abstract: A semiconductor package includes a semiconductor chip structure and a transparent substrate. The semiconductor chip structure includes first and second semiconductor chips. The first semiconductor chip includes a semiconductor substrate including first and second surfaces, a wiring layer, and a through electrode. The first semiconductor chip has a step structure on an edge of the semiconductor chip structure and connected to the second surface. The step structure includes first to fourth steps. The first step includes a first bottom surface and a first lateral surface. The second step includes a second bottom surface and a second lateral surface. The third step includes a third bottom surface and a third lateral surface. The through electrode extends from the second bottom surface toward the wiring layer.

公开(公告)号：US20250081645A1

公开(公告)日：2025-03-06

申请号：US18661946

申请日：2024-05-13

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jungwook LIM

IPC: H01L27/146 ,  H01L23/00 ,  H01L23/522

Abstract: Disclosed is an image sensor comprising a first semiconductor substrate that includes a first pixel region and a second pixel region, a first photoelectric conversion element on the first pixel region, a second photoelectric conversion element on the second pixel region, a first floating diffusion section on the first pixel region, a second floating diffusion section on the second pixel region, a first transfer gate electrode between the first photoelectric conversion element and the first floating diffusion section, a second transfer gate electrode between the second photoelectric conversion element and the second floating diffusion section, a second semiconductor substrate on the first semiconductor substrate, and pixel transistors connected to the first and second photoelectric conversion elements. A width of the second photoelectric conversion element is less than that of the first photoelectric conversion element. At least one of the pixel transistors is on the second semiconductor substrate.

公开(公告)号：US20250081469A1

公开(公告)日：2025-03-06

申请号：US18812283

申请日：2024-08-22

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： KIJOON KIM ,  TAEYOUNG KIM ,  SUHWAN LIM

IPC: H10B51/20 ,  H01L21/28 ,  H01L29/51 ,  H10B51/10

Abstract: A vertical semiconductor device includes: a plurality of insulation patterns on a substrate, the plurality of insulation patterns being spaced apart from each other in a vertical direction; a plurality of channel structures being spaced apart from each other in a first direction, each of the plurality of channel structures including interface insulation patterns, and the plurality of channel structures disposed in a first trench extending in the first direction and passing through the insulation patterns in the vertical direction; a ferroelectric structure on an outer surface of each of the plurality channel structures, the ferroelectric structure protruding in a direction toward a gap between some of the insulation patterns in the vertical direction; and a conductive pattern on a sidewall of the ferroelectric structure, the conductive pattern filling the gap in the vertical direction.

公开(公告)号：US20250081462A1

公开(公告)日：2025-03-06

申请号：US18952236

申请日：2024-11-19

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hauk Han ,  Taeyong Kim ,  Keun Lee ,  Jeonggil Lee ,  Taisoo Lim ,  Hanmei Choi

IPC: H10B43/27 ,  H10B41/10 ,  H10B41/27 ,  H10B43/10

Abstract: A semiconductor device includes gate electrodes stacked and spaced apart from each other in a first direction perpendicular to an upper surface of a substrate; interlayer insulating layers alternately stacked with the gate electrodes on the substrate; channel structures extending through the gate electrodes; and a separation region extending through the gate electrodes in the first direction and extending in a second direction perpendicular to the first direction, wherein each of the gate electrodes comprises a first conductive layer and a second conductive layer sequentially stacked, the second conductive layer including a metal nitride, and wherein the first conductive layer and the second conductive layer are each in physical contact with the separation region.

公开(公告)号：US20250081444A1

公开(公告)日：2025-03-06

申请号：US18610790

申请日：2024-03-20

Applicant: Samsung Electronics Co., Ltd.

Inventor： Bowon YOO ,  Seokhan PARK ,  Gyuhwan OH ,  Jinwoo HAN

IPC: H10B12/00

Abstract: A semiconductor memory device includes a peripheral gate structure, bit lines above the peripheral gate structure, being apart from each other in a first direction, and extending in a second direction different from the first direction, first and second active patterns above the bit lines and apart from each other in the second direction, first and second word lines between the first and active patterns and being adjacent to the first and second active patterns, respectively, a first back gate electrode corresponding to the first word line, the first active pattern being between the first back gate electrode and the first word line, a second back gate electrode corresponding to the second word line, the second active being between the second back gate electrode and the second word line, and a word line shielding structure between the first word line and the second word line.