公开(公告)号：US10074732B1

公开(公告)日：2018-09-11

申请号：US15622902

申请日：2017-06-14

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Xinyuan Dou ,  Hui Zang ,  Hong Yu ,  Yanzhen Wang

IPC: H01L29/00 ,  H01L21/8228 ,  H01L29/66 ,  H01L21/8234 ,  H01L29/78

CPC classification number: H01L29/66818 ,  H01L21/823431 ,  H01L27/0886 ,  H01L29/785

Abstract: One illustrative method disclosed herein includes, among other things, forming first and second fins for a short channel FinFET device (“SCD”) and a long channel FinFET device (“LCD”), performing an oxidation process to form a sacrificial oxide material selectively on the channel portion of one of the first and second fins but not on the channel portion of the other of the first and second fins, removing the sacrificial oxide material from the fin on which it is formed so as to produce a reduced-size channel portion on that fin that is less than the initial size of the channel portion of the other non-oxidized fin, and forming first and second gate structures for the SCD and LCD devices.

公开(公告)号：US10068921B2

公开(公告)日：2018-09-04

申请号：US15157786

申请日：2016-05-18

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Hui Zang

IPC: H01L27/12 ,  H01L21/00 ,  H01L23/528 ,  H01L21/84 ,  H01L21/311 ,  H01L21/3105 ,  H01L21/321 ,  H01L21/768 ,  H01L29/66 ,  H01L29/78 ,  H01L29/417

Abstract: Devices and methods for forming semiconductor devices with self aligned contacts for improved process windows are provided. One method includes, for instance: obtaining a wafer with at least two gates, forming partial spacers adjacent to the at least two gates, and forming at least one contact on the wafer. One intermediate semiconductor device includes, for instance: a wafer with an isolation region, at least two gates disposed on the isolation region, at least one source region disposed on the isolation region, at least one drain region disposed on the isolation region, and at least one contact positioned between the at least two gates, wherein a first portion of the at least one contact engages the at least one source region or the at least one drain region and a second portion of the at least one contact extends above a top surface of the at least two gates.

公开(公告)号：US10068766B2

公开(公告)日：2018-09-04

申请号：US15093310

申请日：2016-04-07

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Hui Zang ,  Min-hwa Chi

IPC: H01L21/033 ,  H01L21/02 ,  H01L21/311 ,  H01L21/8234 ,  H01L21/308 ,  H01L21/3213

Abstract: A method includes, for example, providing a starting semiconductor structure having a plurality of material lines disposed over a hard mask, and the hard mask disposed over a patternable layer, forming a protective layer over a portion of at least one material line, the at least one protected material line and at least one unprotected material line having a same critical dimension, oxidizing the at least one unprotected material line to increase the critical dimension compared to the first critical dimension of the at least one protected material line, and etching at least a portion of the oxidized unprotected material line so that the etched critical dimension of the at least one etched material line is different from the first critical dimension of the at least one protected material line.

公开(公告)号：US10050125B1

公开(公告)日：2018-08-14

申请号：US15676300

申请日：2017-08-14

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Yi Qi ,  Hui Zang ,  Xusheng Wu ,  Hsien-Ching Lo

IPC: H01L29/76 ,  H01L29/66 ,  H01L21/02 ,  H01L21/768 ,  H01L23/535 ,  H01L29/78 ,  H01L29/08

Abstract: Methods of forming a structure for a vertical-transport field-effect transistor and structures for a vertical-transport field-effect transistor. A semiconductor fin is formed on a sacrificial layer, and trench isolation is formed in which the semiconductor fin is embedded. The trench isolation is removed at opposite sidewalls of the semiconductor fin. After the trench isolation is removed at opposite sidewalls of the semiconductor fin, the sacrificial layer is removed to form a cavity extending beneath the semiconductor fin while the semiconductor fin is supported by the trench isolation adjacent to opposite end surfaces of the semiconductor fin. A semiconductor material is formed in the cavity to provide a source/drain region.

公开(公告)号：US09984932B1

公开(公告)日：2018-05-29

申请号：US15345612

申请日：2016-11-08

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Hui Zang ,  Min-hwa Chi

IPC: H01L21/762 ,  H01L21/8234 ,  H01L27/088 ,  H01L29/06 ,  H01L29/66

CPC classification number: H01L21/823431 ,  H01L21/823418 ,  H01L21/823481 ,  H01L27/0886 ,  H01L29/0657 ,  H01L29/66545

Abstract: A finFET includes a source or a drain including: a first semiconductor fin extending parallel to a second semiconductor fin, and a semiconductor connector fin creating a first semiconductor fin loop by connecting an end of the first semiconductor fin to an end of the second semiconductor fin. A diffusion break isolates the source or the drain, and is positioned about the first semiconductor connector fin and the ends of the first semiconductor fin and the second semiconductor fin. The semiconductor connector fin provides an epitaxial growth surface adjacent the diffusion break. A related method and IC structure are also disclosed.

公开(公告)号：US09935112B1

公开(公告)日：2018-04-03

申请号：US15599581

申请日：2017-05-19

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Hui Zang ,  Srikanth Balaji Samavedam

IPC: H01L27/11 ,  H01L27/088

CPC classification number: H01L27/1104 ,  G11C8/16 ,  G11C11/412 ,  H01L27/0207 ,  H01L29/786

Abstract: A static random access memory (SRAM) cell includes 1st and 2nd fins disposed on a substrate. A 1st pass gate transistor (1st PG) is embedded in the 1st fin. The 1st PG has a source region and a drain region disposed over the 1st and 2nd fins. A 1st gate structure (1st PG-G) is disposed over the 1st fin and between the source and drain regions. The 1st PG-G is electrically connected to a 1st word line. A 2nd pass gate transistor (2nd PG) is embedded in the 2nd fin. The 2nd PG has the same source and drain regions. A 2nd gate structure (2nd PG-G) is disposed over the 2nd fin and between the source and drain regions. The 2nd PG-G is electrically connected to a 2nd word line. A 1st CT pillar is disposed between the 1st PG-G and 2nd PG-G.

公开(公告)号：US09935104B1

公开(公告)日：2018-04-03

申请号：US15589292

申请日：2017-05-08

Applicant: GLOBALFOUNDRIES INC.

Inventor： Haiting Wang ,  Wei Zhao ,  Hong Yu ,  Xusheng Wu ,  Hui Zang ,  Zhenyu Hu

IPC: H01L21/84 ,  H01L27/088 ,  H01L21/8234 ,  H01L21/311 ,  H01L29/06 ,  H01L21/308 ,  H01L21/02

CPC classification number: H01L27/0886 ,  H01L21/02164 ,  H01L21/3086 ,  H01L21/31111 ,  H01L21/762 ,  H01L21/823418 ,  H01L21/823431 ,  H01L21/823468 ,  H01L21/823481 ,  H01L29/0649

Abstract: Disclosed is a semiconductor structure, including at least one fin-type field effect transistor and at least one single-diffusion break (SDB) type isolation region, and a method of forming the semiconductor structure. In the method, an isolation bump is formed above an isolation region within a semiconductor fin and sidewall spacers are formed on the bump. During an etch process to reduce the height of the bump and to remove isolation material from the sidewalls of the fin, the sidewall spacers prevent lateral etching of the bump. During an etch process to form source/drain recesses in the fin, the sidewalls spacers protect the semiconductor material adjacent to the isolation region. Consequently, the sides and bottom of each recess include semiconductor surfaces and the angle of the top surfaces of the epitaxial source/drain regions formed therein is minimized, thereby minimizing the risk of unlanded source/drain contacts.

公开(公告)号：US20180069009A1

公开(公告)日：2018-03-08

申请号：US15259472

申请日：2016-09-08

Applicant: GLOBALFOUNDRIES INC.

Inventor： Min-hwa Chi ,  Hui Zang

IPC: H01L27/11 ,  H01L23/535 ,  H01L29/78 ,  H01L29/45 ,  H01L29/66

CPC classification number: H01L27/1104 ,  H01L23/535 ,  H01L29/45 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/785

Abstract: FinFET structures and methods of forming such structures. The FinFET structures including a substrate; at least two gates disposed on the substrate; a plurality of source/drain regions within the substrate adjacent to each of the gates; a dielectric disposed between each gate and the plurality of source/drain regions adjacent to each gate; a dielectric capping layer disposed on a first one of the at least two gates, wherein no dielectric capping layer is disposed on a second one of the at least two gates; and a local interconnect electrically connected to the second one of the at least two gates, wherein the dielectric capping layer disposed on the first one of the at least two gates prevents an electrical connection between the local interconnect and the first one of the at least two gates.

公开(公告)号：US09911736B1

公开(公告)日：2018-03-06

申请号：US15622949

申请日：2017-06-14

Applicant: GLOBALFOUNDRIES INC.

Inventor： Hui Zang ,  Haigou Huang ,  Xiaofeng Qiu

IPC: H01L21/28 ,  H01L27/088 ,  H01L21/8234 ,  H01L29/49 ,  H01L29/66 ,  H01L21/3105 ,  H01L21/762

CPC classification number: H01L21/31053 ,  H01L21/28123 ,  H01L21/76229 ,  H01L21/823431 ,  H01L21/823437 ,  H01L21/823468 ,  H01L21/823475 ,  H01L21/823481 ,  H01L21/823821 ,  H01L21/823828 ,  H01L21/823842 ,  H01L21/823878 ,  H01L27/0886 ,  H01L29/165 ,  H01L29/66545 ,  H01L29/7848 ,  H01L29/785

Abstract: In a method for forming an integrated circuit (IC) structure, which incorporates multiple field effect transistors (FETs) with discrete replacement metal gates (RMGs) and replacement metal contacts (RMCs), gate cut trench(es) and contact cut trench(es) are formed at the same process level. These trench(es) are then filled at the same time with the same isolation material to form gate cut isolation region(s) for electrically isolating adjacent RMGs and contact cut isolation region(s) for electrically isolating adjacent RMCs, respectively. The selected isolation material can be a low-K isolation material for optimal performance. Furthermore, since the same process step is used to fill both types of trenches, only a single chemical mechanical polishing (CMP) process is needed to remove the isolation material from above the gate level, thereby minimizing gate height loss and process variation. Also disclosed herein is an IC structure formed according to the method.

公开(公告)号：US09842927B1

公开(公告)日：2017-12-12

申请号：US15248367

申请日：2016-08-26

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Hui Zang ,  Manfred J Eller ,  Min-Hwa Chi ,  Jerome J. B. Ciavatti

IPC: H01L29/49 ,  H01L29/43 ,  H01L27/092 ,  H01L21/28 ,  H01L29/78 ,  H01L29/66 ,  H01L29/417

CPC classification number: H01L29/783 ,  H01L27/1104 ,  H01L29/41775 ,  H01L29/4975 ,  H01L29/66545 ,  H01L29/66795

Abstract: One aspect of the disclosure relates to an integrated circuit structure. The integrated circuit structure may include: a gate structure between a pair of gate spacers within a dielectric layer and substantially surrounding a fin, wherein the gate structure is disposed adjacent to a channel region within the fin; and a source/drain contact extending within the dielectric layer to a source/drain region within a fin, the source/drain contact being separated from the gate structure by at least one gate spacer in the pair of gate spacers, wherein the channel region and the source/drain region provide electrical connection between the gate structure and the source/drain contact.