公开(公告)号：US20170069764A1

公开(公告)日：2017-03-09

申请号：US15356022

申请日：2016-11-18

Applicant: STMicroelectronics (Crolles 2) SAS

Inventor： Gregory Bidal

IPC: H01L29/786 ,  H01L29/06

CPC classification number: H01L29/78696 ,  H01L21/28026 ,  H01L21/28158 ,  H01L21/7624 ,  H01L29/0649 ,  H01L29/0653 ,  H01L29/0684 ,  H01L29/42364 ,  H01L29/66477 ,  H01L29/665 ,  H01L29/6656 ,  H01L29/66636 ,  H01L29/66772 ,  H01L29/78 ,  H01L29/78603 ,  H01L29/78618 ,  H01L29/78654

Abstract: A MOS transistor includes a semiconductor layer resting on an insulator and having a substantially planar upper surface. The semiconductor layer extends down to a first depth in the channel region, and down to a second depth, greater than the first depth, in the source and drain regions. In the channel region, the semiconductor layer is formed from a portion of an upper semiconductor layer of a silicon on insulator substrate. In the source and drain regions, the semiconductor layer is formed by epitaxially grown semiconductor material.

Abstract translation: MOS晶体管包括搁置在绝缘体上并具有基本平坦的上表面的半导体层。 半导体层在沟道区域中向下延伸到第一深度，并且在源极和漏极区域中向下延伸大于第一深度的第二深度。 在沟道区域中，半导体层由绝缘体上硅衬底的上半导体层的一部分形成。 在源区和漏区中，通过外延生长的半导体材料形成半导体层。

公开(公告)号：US09586207B2

公开(公告)日：2017-03-07

申请号：US14903960

申请日：2014-07-08

Applicant: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES ,  STMICROELECTRONICS (CROLLES 2) SAS

Inventor： Sebastien Mermoz ,  Lea Di Cioccio ,  Thomas Magis ,  Loic Sanchez

IPC: B44C1/22 ,  C03C15/00 ,  C03C25/68 ,  C23F1/00 ,  B01L3/00 ,  B81C1/00 ,  B81C3/00 ,  B81B1/00 ,  H01L23/13 ,  H01L21/3065

CPC classification number: B01L3/561 ,  B01L3/502 ,  B01L2200/12 ,  B01L2300/0838 ,  B81B1/002 ,  B81B2201/058 ,  B81C1/00555 ,  B81C1/00626 ,  B81C3/005 ,  B81C2201/0112 ,  H01L21/30655 ,  H01L23/13 ,  H01L2224/95146

Abstract: A method for capillary self-assembly of a plate and a carrier, including: forming an etching mask on a region of a substrate; reactive-ion etching the substrate, the etching using a series of cycles each including isotropic etching followed by surface passivation, wherein a duration of the isotropic etching for each cycle increases from one cycle to another, a ratio between durations of the passivation and etching of each cycle is lower than a ratio for carrying out a vertical anisotropic etching to form a carrier having an upper surface defined by the region and side walls defining an acute angle with the upper surface; removing the etching mask; placing a droplet on the upper surface of the carrier; and placing the plate on the droplet.

Abstract translation: 一种用于板和载体的毛细管自组装的方法，包括：在衬底的区域上形成蚀刻掩模; 反应离子蚀刻衬底，蚀刻使用一系列循环，每个循环包括各向同性蚀刻，然后进行表面钝化，其中每个循环的各向同性蚀刻的持续时间从一个循环增加到另一个周期，钝化和蚀刻的持续时间之间的比率 每个周期低于进行垂直各向异性蚀刻的比例，以形成具有由与上表面限定锐角的区域和侧壁限定的上表面的载体; 去除蚀刻掩模; 在载体的上表面上放置液滴; 并将板放在液滴上。

公开(公告)号：US20170062424A1

公开(公告)日：2017-03-02

申请号：US15234240

申请日：2016-08-11

Applicant: Commissariat a L'Energie Atomique et aux Energies Alternatives ,  STMicroelectronics (Crolles 2) SAS

Inventor： Philippe RODRIGUEZ ,  Elodie GHEGIN ,  Fabrice NEMOUCHI

IPC: H01L27/092 ,  H01L21/768 ,  H01L21/02 ,  H01L21/8234 ,  H01L29/161 ,  H01L29/45 ,  H01L21/8238 ,  H01L21/324 ,  H01L29/66

CPC classification number: H01L27/092 ,  H01L21/02068 ,  H01L21/02532 ,  H01L21/02631 ,  H01L21/28525 ,  H01L21/2855 ,  H01L21/28568 ,  H01L21/324 ,  H01L21/76843 ,  H01L21/76855 ,  H01L21/76879 ,  H01L21/76897 ,  H01L21/823475 ,  H01L21/823814 ,  H01L21/823871 ,  H01L21/8258 ,  H01L29/161 ,  H01L29/45 ,  H01L29/66568

Abstract: A production of contact zones for a transistor device including the steps of: a) forming at least one layer made of a compound based on semiconductor and metal on one or more first semiconductor region(s) of a first N-type transistor and on one or more second semiconductor region(s) of a second P-type transistor resting on a same substrate, the first regions being based on a III-V type material whereas the second semiconductor regions are based on another material different from the III-V material, the semiconductor of the compound being an N-type dopant of the III-V material, b) carrying out at least one thermal annealing so as to form on the first semiconductor regions first contact zones and on the second semiconductor regions second contact zones based on a semiconductor and metal compound while increasing the N-doping of the III-V material.

公开(公告)号：US20170059893A1

公开(公告)日：2017-03-02

申请号：US14836011

申请日：2015-08-26

Applicant: STMICROELECTRONICS (CROLLES 2) SAS ,  STMICROELECTRONICS SA

Inventor： Patrick LEMAITRE ,  Jean-Francois CARPENTIER ,  Charles BAUDOT ,  Jean-Robert MANOUVRIER

IPC: G02F1/025 ,  G02B6/293

CPC classification number: G02F1/225 ,  G02F1/025 ,  G02F1/2257 ,  G02F2001/212 ,  G02F2203/15

Abstract: An electro-optic (E/O) device includes an asymmetric optical coupler having an input and first and second outputs, a first optical waveguide arm coupled to the first output of the first asymmetric optical coupler, and a second optical waveguide arm coupled to the second output of the first asymmetric optical coupler. At least one E/O amplitude modulator is coupled to at least one of the first and second optical waveguide arms. An optical combiner is coupled to the first and second optical waveguide arms downstream from the at least one E/O amplitude modulator.

Abstract translation: 电光（E / O）装置包括具有输入和第一和第二输出的不对称光耦合器，耦合到第一非对称光耦合器的第一输出的第一光波导臂和耦合到第一和第二输出的第二光波导臂 第二非对称光耦合器的第二输出。 至少一个E / O振幅调制器耦合到第一和第二光波导臂中的至少一个。 光合成器耦合到至少一个E / O振幅调制器下游的第一和第二光波导臂。

公开(公告)号：US09530489B2

公开(公告)日：2016-12-27

申请号：US14527166

申请日：2014-10-29

Applicant: STMICROELECTRONICS (CROLLES 2) SAS

Inventor： Pierre Caubet ,  Mickael Gros-Jean

IPC: G11C7/00 ,  G11C11/42 ,  G11C13/04 ,  G02F1/163 ,  G02F1/15 ,  G02F3/02

CPC classification number: G11C11/42 ,  G02F1/15 ,  G02F1/1523 ,  G02F1/1525 ,  G02F1/1527 ,  G02F1/163 ,  G02F3/022 ,  G02F2001/1512 ,  G02F2001/1635 ,  G02F2201/58 ,  G11C7/00 ,  G11C13/04

Abstract: A memory device may include an access transistor, and a memory cell configured to store an item of information. The memory cell may include first and second electrodes configured to have different optoelectronic states corresponding respectively to two values of the item of information, and to switch between the different optoelectronic states based upon a control signal external to the memory cell, the different optoelectronic states being naturally stable in an absence of the control signal. The memory cell may also include a solid electrolyte between the first and second electrodes.

Abstract translation: 存储器件可以包括存取晶体管，以及被配置为存储信息项的存储单元。 存储单元可以包括被配置为具有分别对应于信息项的两个值的不同光电子状态的第一和第二电极，以及基于存储单元外部的控制信号在不同的光电子态之间切换，不同的光电子态是 在没有控制信号的情况下自然稳定。 存储单元还可以包括在第一和第二电极之间的固体电解质。

公开(公告)号：US09520334B2

公开(公告)日：2016-12-13

申请号：US14155007

申请日：2014-01-14

Applicant: STMicroelectronics SA ,  STMicroelectronics (Crolles 2) SAS ,  Anne Lombardot

Inventor： Laurent-Luc Chapelon ,  Pascal Ancey ,  Sandrine Lhostis

IPC: H01L23/34 ,  H01L23/36 ,  H01L23/427 ,  H01L23/433 ,  H01L25/065 ,  H01L23/31 ,  H01L23/48 ,  H01L29/06

CPC classification number: H01L23/36 ,  H01L23/3128 ,  H01L23/4275 ,  H01L23/4334 ,  H01L23/481 ,  H01L25/0657 ,  H01L29/0657 ,  H01L2224/73204 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06555 ,  H01L2225/06589

Abstract: An integrated structure includes a support supporting at least one chip and a heat dissipating housing, attached to the chip. The housing is thermally conductive and has a thermal expansion compatible with the chip. The housing may further including closed cavities filled with a phase change material.

Abstract translation: 集成结构包括支撑至少一个芯片的支撑件和附接到芯片的散热壳体。 壳体是导热的并具有与芯片兼容的热膨胀。 壳体还可以包括填充有相变材料的封闭空腔。

公开(公告)号：US20160351661A1

公开(公告)日：2016-12-01

申请号：US14962193

申请日：2015-12-08

Applicant: STMicroelectronics (Crolles 2) SAS

Inventor： Stephane Monfray ,  Thomas Skotnicki

IPC: H01L29/06 ,  H01L29/78 ,  H01L21/02 ,  H01L29/66 ,  H01L29/165 ,  H01L29/423 ,  H01L21/762

CPC classification number: H01L29/0649 ,  H01L21/02532 ,  H01L21/76264 ,  H01L29/0692 ,  H01L29/165 ,  H01L29/42376 ,  H01L29/66568 ,  H01L29/66795 ,  H01L29/78 ,  H01L29/7853 ,  H01L29/78696

Abstract: An integrated circuit includes a substrate with an isolation region that bounds a zone. A transistor includes a concave semiconductor region that is supported by the isolation region in a first direction and has a concavity turned to face towards the zone. The concave semiconductor region contains drain, source and channel regions. A gate region for the transistor possesses a concave portion overlapping a portion of the concave semiconductor region. A dielectric region is located between the zone of the substrate and the concave semiconductor region.

Abstract translation: 集成电路包括具有限定区域的隔离区域的衬底。 晶体管包括凹形半导体区域，该半导体区域在第一方向上由隔离区域支撑并且具有朝向该区域的凹面。 凹入半导体区域包含漏极，源极和沟道区域。 晶体管的栅极区域具有与凹入半导体区域的一部分重叠的凹部。 电介质区域位于衬底的区域和凹形半导体区域之间。

公开(公告)号：US09507089B2

公开(公告)日：2016-11-29

申请号：US14804629

申请日：2015-07-21

Applicant: STMICROELECTRONICS SA ,  STMICROELECTRONICS (CROLLES 2) SAS

Inventor： Alain Chantre ,  Sébastien Cremer

IPC: G02B6/12 ,  G02B6/10 ,  C03B37/022 ,  H01L21/00 ,  H01L31/102 ,  G02B6/136 ,  H01S5/343 ,  H01S5/026 ,  H01S5/02 ,  G02B6/132 ,  G02B6/42

CPC classification number: G02B6/136 ,  G02B6/12004 ,  G02B6/132 ,  G02B6/4257 ,  G02B2006/121 ,  G02B2006/12121 ,  H01S5/0085 ,  H01S5/021 ,  H01S5/02248 ,  H01S5/026 ,  H01S5/343

Abstract: A method of manufacturing an integrated circuit including photonic components on a silicon layer and a laser made of a III-V group material includes providing the silicon layer positioned on a first insulating layer that is positioned on a support. First trenches are etched through the silicon layer and stop on the first insulating layer, and the first trenches are covered with a silicon nitride layer. Second trenches are etched through a portion of the silicon layer, and the first and second trenches are filled with silicon oxide, which are planarized. The method further includes removing the support and the first insulating layer, and bonding a wafer including a III-V group heterostructure on the rear surface of the silicon layer.

Abstract translation: 制造包括硅层上的光子分量和由III-V族材料制成的激光的集成电路的方法包括提供位于位于支撑体上的第一绝缘层上的硅层。 第一沟槽被蚀刻穿过硅层并在第一绝缘层上停止，并且第一沟槽被氮化硅层覆盖。 第二沟槽被蚀刻通过硅层的一部分，并且第一和第二沟槽用平坦化的氧化硅填充。 该方法还包括去除支撑体和第一绝缘层，以及在硅层的后表面上接合包括III-V族异质结构的晶片。

公开(公告)号：US20160276480A1

公开(公告)日：2016-09-22

申请号：US15169495

申请日：2016-05-31

Applicant: STMICROELECTRONICS, INC. ,  STMICROELECTRONICS (CROLLES 2) SAS

Inventor： Qing LIU ,  Thomas SKOTNICKI

IPC: H01L29/78 ,  H01L21/28 ,  H01L29/66 ,  H01L29/06 ,  H01L29/10

CPC classification number: H01L29/7838 ,  H01L21/28114 ,  H01L27/1203 ,  H01L29/0649 ,  H01L29/0653 ,  H01L29/0847 ,  H01L29/1033 ,  H01L29/42356 ,  H01L29/66477 ,  H01L29/66545 ,  H01L29/66575 ,  H01L29/66628 ,  H01L29/66651 ,  H01L29/7834

Abstract: An integrated circuit die includes a substrate having a first layer of semiconductor material, a layer of dielectric material on the first layer of semiconductor material, and a second layer of semiconductor material on the layer of dielectric material. An extended channel region of a transistor is positioned in the second layer of semiconductor material, interacting with a top surface, side surfaces, and potentially portions of a bottom surface of the second layer of semiconductor material. A gate dielectric is positioned on a top surface and on the exposed side surface of the second layer of semiconductor material. A gate electrode is positioned on the top surface and the exposed side surface of the second layer of semiconductor material.

公开(公告)号：US09437674B2

公开(公告)日：2016-09-06

申请号：US14660601

申请日：2015-03-17

Applicant: STMicroelectronics (Crolles 2) SAS

Inventor： Nayera Ahmed ,  François Roy

IPC: H01L29/06 ,  H01L21/762 ,  H01L21/763

CPC classification number: H01L29/0649 ,  H01L21/76202 ,  H01L21/76205 ,  H01L21/76224 ,  H01L21/76227 ,  H01L21/76229 ,  H01L21/763

Abstract: A method of manufacturing an insulating trench including the successive steps of: a) forming, on a semiconductor substrate, a first masking structure including a layer of a first selectively-etchable material and etching a trench into the substrate; b) forming an insulating coating on the trench walls and filling the trench with doped polysilicon; c) forming a silicon oxide plug penetrating into the trench substantially all the way to the upper surface of the substrate and protruding above the upper surface of the substrate; and d) removing the layer of the first material.

Abstract translation: 一种制造绝缘沟槽的方法，包括以下连续步骤：a）在半导体衬底上形成包括第一可选蚀刻材料层的第一掩模结构，并将沟槽蚀刻到衬底中; b）在沟槽壁上形成绝缘涂层并用掺杂多晶硅填充沟槽; c）形成贯穿所述沟槽的氧化硅插塞，其基本上一直延伸到所述衬底的上表面并突出到所述衬底的上表面上方; 和d）去除第一材料的层。