公开(公告)号：US09818689B1

公开(公告)日：2017-11-14

申请号：US15137362

申请日：2016-04-25

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Hui Zang ,  Min-hwa Chi

IPC: H01L23/52 ,  H01L23/522 ,  H01L23/528 ,  H01L49/02

CPC classification number: H01L23/5223 ,  H01L23/5226 ,  H01L23/528 ,  H01L28/60

Abstract: A method of forming a semiconductor structure, comprising forming a dual damascene structure having a capacitor trench and an interconnect trench, forming a first electrode a dielectric of the capacitor, and, depositing a metal within said capacitor trench and said interconnection trench wherein the metal forms a second electrode of the capacitor and also forms an interconnection between layers of an interconnecting structure of a semiconductor device. A semiconductor structure, comprising a dual damascene structure having a capacitor trench for a capacitor, the capacitor including a first electrode, a second electrode, and a high-K dielectric between the first and second electrodes, the high-k dielectric configured to seal the first electrode from the second electrode and from subsequent wiring layers of the interconnecting structure of the semiconductor device, and, an interconnection trench for a metal interconnection to form an interconnection between the interconnecting structure of the semiconductor device.

公开(公告)号：US09799661B1

公开(公告)日：2017-10-24

申请号：US15397004

申请日：2017-01-03

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Hui Zang ,  Manfred Eller ,  Min-hwa Chi

IPC: H01L27/108 ,  H01L27/11 ,  H01L29/49 ,  H01L29/06 ,  H01L21/84 ,  H01L21/762 ,  G11C11/419

CPC classification number: H01L27/1104 ,  G11C11/412 ,  G11C11/419 ,  H01L21/76283 ,  H01L29/0649

Abstract: Static random access memory (SRAM) bitcell structures with improved minimum operation voltage (Vmin) and yield are provided. The structures may include a silicon substrate, a deep n-well (DNW) layer, p-well (PW) regions, doped back-plate (BP) regions, a buried oxide (BOX) layer, and/or active regions formed on the BOX layer and over portions of the BP regions. At least one BP region may extend below at least one shallow trench isolation (STI) region, at least one contact to back plate (CBP), at least one active region and at least one PC construct overlapping the at least one active region forming a channel of at least one of a first pull-down (PD1) transistor and a second pull-down (PD2) transistor. The at least one CBP facilitates biasing at least one of the PD1 and PD2 transistors during at least one of a read, write or standby operation of the structures.

公开(公告)号：US09773680B1

公开(公告)日：2017-09-26

申请号：US15377503

申请日：2016-12-13

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Hui Zang ,  Jinping Liu

IPC: H01L21/311 ,  H01L21/3065 ,  H01L29/66 ,  H01L21/02 ,  H01L21/308 ,  H01L27/11

CPC classification number: H01L21/3065 ,  H01L21/02532 ,  H01L21/02592 ,  H01L21/0337 ,  H01L21/3081 ,  H01L21/3085 ,  H01L21/823431 ,  H01L27/1104 ,  H01L29/66553

Abstract: Devices and methods of fabricating scaled SRAM with flexible active pitch are provided. One method includes, for instance: obtaining an intermediate semiconductor device having a first portion and a second portion, including a plurality of layers and a patterned mandrel; forming a first set of spacers surrounding the patterned mandrel; etching the dielectric layer; depositing a photoresist layer; opening the photoresist layer over the first portion and not the second portion, removing the patterned mandrel in the open areas; etching the dielectric layer in the open areas; removing the photoresist layer, the remaining patterned mandrels, and the first set of spacers in the first and second portion, etching the silicon layer and MTO layer to form a pattern; forming a second set of spacers around the pattern; and etching a set of fins into the substrate and oxide layer.

公开(公告)号：US09761480B1

公开(公告)日：2017-09-12

申请号：US15047137

申请日：2016-02-18

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Xusheng Wu ,  Hui Zang

IPC: H01L21/762 ,  H01L21/84 ,  H01L21/308 ,  H01L21/3213 ,  H01L21/311 ,  H01L29/08 ,  H01L29/06 ,  H01L27/12

CPC classification number: H01L21/76283 ,  H01L21/308 ,  H01L21/31111 ,  H01L21/32139 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/0649 ,  H01L29/0847

Abstract: One illustrative method disclosed includes forming an isolation structure so as to define first and second active regions on the SOI substrate, forming a field effect transistor above the first active region and forming an opening in the second active region that exposes an upper surface of the bulk semiconductor layer in the second active region. In this example, the method further includes performing a common epitaxial growth process so as to form an epi semiconductor material region above each of the source/drain regions of the transistor and to form a unitary epi semiconductor structure above the second active region, wherein the unitary epi semiconductor structure is formed on and in contact with the exposed upper surface of the bulk semiconductor layer within the opening and on and in contact with an upper surface of the active layer in the second active region.

公开(公告)号：US09734897B1

公开(公告)日：2017-08-15

申请号：US15397021

申请日：2017-01-03

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Hui Zang ,  Manfred Eller ,  Min-hwa Chi

IPC: G11C11/00 ,  G11C11/419 ,  H01L27/11 ,  H01L23/522 ,  H01L21/762 ,  G11C11/412

CPC classification number: G11C11/419 ,  G11C11/412 ,  H01L21/76224 ,  H01L27/0207 ,  H01L27/11 ,  H01L27/1104

Abstract: Static random access memory (SRAM) bitcell structures with improved minimum operation voltage (Vmin) and yield are provided. The structures may include a silicon substrate, a deep n-well (DNW) layer, p-well (PW) regions, doped back-plate (BP) regions, a buried oxide (BOX) layer, and/or active regions formed on the BOX layer and over portions of the BP regions. At least one BP region may extend below at least one shallow trench isolation (STI) region, at least one contact to back plate (CBP), at least one active region and at least one PC construct overlapping the at least one active region forming a channel of at least one of a first pass gate (PG1) transistor and a second pass gate (PG2) transistor. The at least one CBP facilitates biasing of at least one the PG1 and PG2 transistors during at least one of a read, write or standby operation of the structures.

公开(公告)号：US20170141214A1

公开(公告)日：2017-05-18

申请号：US15343821

申请日：2016-11-04

Applicant: GLOBALFOUNDRIES INC.

Inventor： Hui Zang ,  Min-Hwa Chi ,  Jinping Liu

IPC: H01L29/66 ,  H01L29/78 ,  H01L21/02 ,  H01L29/08 ,  H01L21/306

CPC classification number: H01L29/66795 ,  H01L21/02532 ,  H01L21/0262 ,  H01L21/30604 ,  H01L29/0847 ,  H01L29/785

Abstract: At least one method, apparatus and system disclosed herein fin field effect transistor (finFET) comprising a tall fin having a plurality of epitaxial regions. A first fin of a transistor is formed. The first fin comprising a first portion comprising silicon, a second portion comprising silicon germanium and a third portion comprising silicon. A gate structure above the third portion is formed. An etching process is performed for removing the silicon germanium of the second portion that is not below the gate structure. A first epitaxy region is formed above the first portion. A second epitaxy region is formed vertically aligned with the first epitaxy region and above the second region.

公开(公告)号：US09620425B1

公开(公告)日：2017-04-11

申请号：US15156822

申请日：2016-05-17

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Hui Zang ,  Min-hwa Chi ,  Jinping Liu

IPC: H01L21/8234 ,  H01L21/84 ,  H01L29/423 ,  H01L29/49

CPC classification number: H01L27/0886 ,  H01L21/823431

Abstract: A method of adjusting work-function metal thickness includes providing a semiconductor structure having a substrate, the substrate including a first array of fins formed thereon. First spacers are formed having a first spacer thickness on sidewalls of fins of the first array. The thickness of the first spacers is adjusted to provide a second spacer thickness different from the first spacer thickness. First supports are formed between and adjacent the first spacers. The first spacers are removed to form first WF metal trenches defined by the fins of the first array and the first supports. A gate is formed extending laterally across the fins of the first array. First WF metal structures are disposed within the first WF metal trenches within the gate.

公开(公告)号：US09601495B2

公开(公告)日：2017-03-21

申请号：US14814322

申请日：2015-07-30

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Hui Zang ,  Min-hwa Chi

IPC: H01L27/10 ,  H01L29/66 ,  H01L27/108

CPC classification number: H01L27/10826 ,  H01L27/1085 ,  H01L27/10879 ,  H01L27/10888 ,  H01L28/90 ,  H01L29/66545

Abstract: A three-dimensional semiconductor device includes a semiconductor substrate, fin(s) coupled to the substrate and surrounded at a bottom portion thereof by isolation material, each fin including a source region, a drain region and a channel region therebetween, a first gate and spacers over a portion of each fin, and a second gate and spacers, the second gate encompassing a common end portion of each fin. The first gate and corresponding source and drain regions act as an access transistor, and the second gate and common end portion(s) of the fin(s) act as a storage capacitor, and a top surface of the second gate acts as a plate for the storage capacitor, when multiple cells are arranged in an array.

公开(公告)号：US09564484B2

公开(公告)日：2017-02-07

申请号：US14983157

申请日：2015-12-29

Applicant: GLOBALFOUNDRIES INC.

Inventor： Hui Zang ,  Bingwu Liu

IPC: H01L21/02 ,  H01L49/02 ,  H01L23/522 ,  H01L23/532

CPC classification number: H01L28/60 ,  H01L23/5223 ,  H01L23/5226 ,  H01L23/53228 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Embodiments of the present invention provide improved metal-insulator-metal (MIM) capacitors. In embodiments, series resistance is reduced by forming a via underneath the bottom plate of a MIM capacitor, leading to a metallization layer or intermediate metal sublayer. In embodiments, the MIM capacitor is formed with a corrugated shape to increase the plate surface area, allowing a thicker dielectric to be used, thereby mitigating leakage issues.

Abstract translation: 本发明的实施例提供改进的金属 - 绝缘体 - 金属（MIM）电容器。 在实施例中，通过在MIM电容器的底板下面形成通孔，导致金属化层或中间金属子层来减小串联电阻。 在实施例中，MIM电容器形成为波纹形状以增加板表面积，允许使用更厚的电介质，从而减轻漏电问题。

公开(公告)号：US09564440B2

公开(公告)日：2017-02-07

申请号：US15232246

申请日：2016-08-09

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION ,  GLOBALFOUNDRIES INC.

Inventor： Hyun-Jin Cho ,  Tenko Yamashita ,  Hui Zang

IPC: H01L27/092 ,  H01L29/66 ,  H01L29/49 ,  H01L29/423 ,  H01L21/8238

CPC classification number: H01L29/512 ,  H01L21/02532 ,  H01L21/0262 ,  H01L21/28088 ,  H01L21/823814 ,  H01L21/823821 ,  H01L21/823828 ,  H01L21/823842 ,  H01L21/823864 ,  H01L21/845 ,  H01L27/0922 ,  H01L27/0924 ,  H01L27/1211 ,  H01L29/42364 ,  H01L29/42376 ,  H01L29/4238 ,  H01L29/4958 ,  H01L29/4966 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/66795 ,  H01L29/785 ,  H01L29/7851

Abstract: A method of forming a gate structure for a semiconductor device that includes forming first spacers on the sidewalls of replacement gate structures that are present on a fin structure, wherein an upper surface of the first spacers is offset from an upper surface of the replacement gate structure, and forming at least second spacers on the first spacers and the exposed surfaces of the replacement gate structure. The method may further include substituting the replacement gate structure with a functional gate structure having a first width portion in a first space between adjacent first spacers, and a second width portion having a second width in a second space between adjacent second spacers, wherein the second width is greater than the first width.

Abstract translation: 一种形成用于半导体器件的栅极结构的方法，包括在存在于鳍状结构上的置换栅极结构的侧壁上形成第一间隔物，其中第一间隔物的上表面偏离替换栅极结构的上表面 并且在所述第一间隔物和所述替换栅极结构的所述暴露表面上形成至少第二间隔物。 该方法还可以包括用相邻的第一间隔件之间的第一空间中具有第一宽度部分的功能栅极结构代替替换栅极结构，以及在相邻的第二间隔物之间​​的第二空间中具有第二宽度的第二宽度部分，其中第二 宽度大于第一宽度。