公开(公告)号：US5844404A

公开(公告)日：1998-12-01

申请号：US720491

申请日：1996-09-30

Applicant: Fabio Tassan Caser ,  Stefan Schippers ,  Marcello Cane

Inventor： Fabio Tassan Caser ,  Stefan Schippers ,  Marcello Cane

IPC: G11C5/14 ,  G11C16/30 ,  G05F3/24

CPC classification number: G11C16/30 ,  G11C5/147

Abstract: A voltage regulator for electrically programmable non-volatile memory cells includes a gain stage which is supplied a voltage from a voltage booster connected to a supply voltage reference, having an input terminal connected to an output of a voltage divider and an output terminal connected to a pull-up transistor of a pull-up and pull-down differential pair to output the regulated voltage for programming at least one column or bit line of the memory cells. The voltage regulator also includes a second gain stage having an input terminal connected to a second output of the voltage divider. The second stage has an output connected to turn on the pull-down transistor in the complementary pair upon the regulated voltage exceeding a predetermined value.

Abstract translation: 用于电可编程非易失性存储单元的电压调节器包括增益级，其从连接到电源电压基准的升压器提供电压，其具有连接到分压器的输出的输入端子和连接到 上拉和下拉差分对的上拉晶体管输出调节电压，用于对存储单元的至少一列或位线进行编程。 电压调节器还包括具有连接到分压器的第二输出的输入端的第二增益级。 第二级具有连接的输出端，以便在调节电压超过预定值时，互补对中的下拉晶体管导通。

公开(公告)号：US5844388A

公开(公告)日：1998-12-01

申请号：US828167

申请日：1997-03-18

Applicant: Giuseppe Maiocchi

Inventor： Giuseppe Maiocchi

IPC: H02P6/10 ,  H02P6/34 ,  H02P23/00 ,  H03B28/00 ,  H03L7/06

CPC classification number: H02P6/10 ,  H02P23/0077 ,  H02P6/34 ,  Y10S388/904

Abstract: The torque characteristic of an electrically driven brushless motor may be optimized by driving the phase windings of the motor with predefined, digitized and stored current or voltage profiles. Appropriate sequences of digital samples of the predefined driving profile are sequentially read from a nonvolatile memory where they are permanently stored to drive, through a DAC, the relative winding of the motor in synchronism with a signal representative of the rotor position.

Abstract translation: 可以通过用预定义的，数字化和存储的电流或电压曲线来驱动电动机的相绕组来优化电驱动的无刷电动机的转矩特性。 从非易失性存储器中顺序地读取预定义驱动简档的数字样本的适当序列，其中它们被永久存储，以通过DAC与代表转子位置的信号同步地驱动马达的相对绕组。

公开(公告)号：US5841167A

公开(公告)日：1998-11-24

申请号：US772657

申请日：1996-12-23

Applicant: Antonio Grimaldi ,  Antonino Schillaci ,  Ferruccio Frisina ,  Giuseppe Ferla

Inventor： Antonio Grimaldi ,  Antonino Schillaci ,  Ferruccio Frisina ,  Giuseppe Ferla

IPC: H01L21/336 ,  H01L23/482 ,  H01L29/06 ,  H01L29/10 ,  H01L29/417 ,  H01L29/423 ,  H01L29/78 ,  H01L29/76 ,  H01L29/94 ,  H01L31/062 ,  H01L31/113

CPC classification number: H01L29/66712 ,  H01L23/4824 ,  H01L29/0696 ,  H01L29/1095 ,  H01L29/4238 ,  H01L29/7802 ,  H01L29/41725 ,  H01L2924/0002

Abstract: A MOS-gated power device integrated structure comprises a plurality of elementary units formed in a semiconductor material layer of a first conductivity type. Each elementary unit is formed in a body stripe of a second conductivity type. There are a plurality of body stripes of the second conductivity type extending substantially in parallel to each other and at least one source region of the first conductivity type disposed within each body stripe. A conductive gate layer is insulatively disposed over the semiconductor material layer between the body stripes in the form of a first web structure. A second web structure of the second conductivity type is formed in the semiconductor material layer and comprises an annular frame portion surrounding the plurality of bodystripes and at least one first elongated stripe extending between two sides of the annular frame portion in a direction substantially orthogonal to the body stripes and that is merged at each end with the annular frame portion. The body stripes are divided by the at least one first elongated stripe into at least two groups of body stripes, wherein one end of each body stripe is merged with the annular frame portion of the second conductivity type and the other end is merged with the at least one first elongated stripe. A conductive gate finger is insulatively disposed above the first elongated stripe and is part of the first web structure. A conductive gate ring surrounds the conductive gate layer and the conductive gate finger and completes the first web structure. A metal gate finger is disposed above the conductive gate finger and is merged at its ends with a metal gate ring structure disposed above the conductive gate ring to provide a third web structure. Source metal plates cover the at least two groups of body stripes and contact each source region and each body stripe to form a source electrode of the power device. A bottom surface of the semiconductor material layer forms a drain of the power device.

公开(公告)号：US5815457A

公开(公告)日：1998-09-29

申请号：US659665

申请日：1996-06-06

Applicant: Luigi Pascucci

Inventor： Luigi Pascucci

IPC: G11C11/413 ,  G11C8/10 ,  G11C8/00

CPC classification number: G11C8/10

Abstract: A bit line selection decoder for an electronic memory having a plurality of bit lines in a plurality of groups includes a first set of a plurality of switches, each switch for selecting one of the plurality of bit lines in response to a control signal from a set of control lines applied to each group of bit lines. A second set of a plurality of switches is provided wherein each switch selects one group of the plurality of bit lines. The bit line selection decoder also includes a decoder which has a first input bus of control lines and a second input bus of control lines, wherein the control lines from the first and second input bus address any one of the plurality of groups of bit lines. The decoder has a plurality of outputs, wherein each output drives one switch in the second set of switches. The decoder may include a plurality of modules. Each module has a first input connected to receive one of the control lines from the second bus and a second input connected to receive the control lines of the first bus. The module includes a mechanism for activating a first output according to a combination of the first input and one of the control lines from the second input and a mechanism for activating a second output according to a combination of the first input and another of the control lines from the second input.

Abstract translation: 一种用于具有多个组中的多个位线的电子存储器的位线选择解码器包括多个开关的第一组，每个开关用于响应于来自一组的控制信号来选择多个位线之一 的控制线应用于每组位线。 提供了第二组多个开关，其中每个开关选择多个位线中的一组。 位线选择解码器还包括具有控制线的第一输入总线和控制线的第二输入总线的解码器，其中来自第一和第二输入总线的控制线寻址多组位线中的任意一组。 解码器具有多个输出，其中每个输出驱动第二组开关中的一个开关。 解码器可以包括多个模块。 每个模块具有连接以从第二总线接收控制线之一的第一输入和连接以接收第一总线的控制线的第二输入。 该模块包括用于根据来自第二输入的第一输入和控制线中的一个的组合来激活第一输出的机构，以及用于根据第一输入和另一个控制线的组合来激活第二输出的机构 从第二个输入。

公开(公告)号：US5812017A

公开(公告)日：1998-09-22

申请号：US567328

申请日：1995-12-05

Applicant: Carla Golla ,  William Vespi

Inventor： Carla Golla ,  William Vespi

IPC: G05F1/46 ,  G11C5/14 ,  H02M3/07 ,  G05F1/10

CPC classification number: G05F1/465 ,  G11C5/145 ,  H02M3/07

Abstract: A charge pump voltage booster circuit with control feedback of the type comprising an output line connected to a load and on which is produced an output voltage boosted in relation to a supply voltage and a feedback loop incorporating a charge pump connected to said line and a control logic circuit of said pump interlocked with a comparator having an input connected to the line comprises also an auxiliary charge pump connected in turn to said line and designed to supply a quantity of current greater than or equal to the leakage currents of the load in stand-by condition. The auxiliary pump has current consumption much lower than that of the main charge pump. In addition, upon emerging from the off state there is provided starting of the main charge pump for a brief time period sufficient to take the booster output to a sufficient value.

Abstract translation: 一种具有控制反馈的电荷泵升压电路，其包括连接到负载的输出线，并且在其上产生相对于电源电压升压的输出电压和包括连接到所述线路的电荷泵的反馈回路和控制 与具有连接到该线路的输入的比较器互锁的所述泵的逻辑电路还包括依次连接到所述线路的辅助电荷泵，并被设计成提供大于或等于负载的静态电流的电流量， 按条件。 辅助泵的电流消耗远低于主电荷泵。 此外，当从关闭状态出来时，提供主电荷泵的启动短暂的时间段，足以使增压器输出达到足够的值。

公开(公告)号：US5811994A

公开(公告)日：1998-09-22

申请号：US671709

申请日：1996-06-28

Applicant: Giulio Ricotti ,  Roberto Bardelli ,  Domenico Rossi

Inventor： Giulio Ricotti ,  Roberto Bardelli ,  Domenico Rossi

IPC: G06K19/07 ,  H03K17/687 ,  H03K19/20

CPC classification number: H03K17/6874 ,  G06K19/0723 ,  H03K17/6872

Abstract: The switch of this invention has two conduction terminals and basically consists of the parallel coupling, across the two conduction terminals, of a first N-channel MOS transistor and second P-channel MOS transistor. The first MOS transistor will be conducting when the signal applied to the conduction terminals has a first polarity, and the second MOS transistor will be conducting when the signal applied to the conduction terminals has a second polarity. Advantageously, if two unidirectional conduction circuit elements are respectively connected in series with the main conduction paths of the two MOS transistors, the drain/body junctions of the latter will never be conducting regardless of the way the switch is connected.

Abstract translation: 本发明的开关具有两个导通端子，并且基本上由跨越两个导通端子的并联耦合的第一N沟道MOS晶体管和第二P沟道MOS晶体管组成。 当施加到导电端子的信号具有第一极性时，第一MOS晶体管将导通，并且当施加到导电端子的信号具有第二极性时，第二MOS晶体管将导通。 有利的是，如果两个单向导通电路元件分别与两个MOS晶体管的主导通路径串联连接，则无论连接开关的方式如何，后者的漏/体接合将永远不会导通。

公开(公告)号：US5808971A

公开(公告)日：1998-09-15

申请号：US726075

申请日：1996-10-03

Applicant: Roberto Alini ,  Melchiorre Bruccoleri ,  Gaetano Cosentino ,  Marco Demicheli

Inventor： Roberto Alini ,  Melchiorre Bruccoleri ,  Gaetano Cosentino ,  Marco Demicheli

IPC: G11B20/14 ,  H03K17/14 ,  H03K17/28 ,  G04F37/00

CPC classification number: H03K17/14 ,  H03K17/28 ,  G11B20/1403

Abstract: A temperature-compensated high-speed timing circuit, which is particularly advantageous in read-interface circuits for disk-drive interface. The voltage on the integrating capacitor is compared against a voltage defined by the drop, on a resistor, induced by a current which is the combination of a reference current from a reference current generator with a temperature-dependent current from another current generator.

公开(公告)号：US5805015A

公开(公告)日：1998-09-08

申请号：US629320

申请日：1996-04-08

Applicant: Melchiorre Bruccoleri ,  Gaetano Cosentino ,  Marco Demicheli ,  Giuseppe Patti

Inventor： Melchiorre Bruccoleri ,  Gaetano Cosentino ,  Marco Demicheli ,  Giuseppe Patti

IPC: G05F3/22 ,  G05F3/26 ,  H03F3/343 ,  H03K17/04 ,  H03K17/60 ,  G05F3/16

CPC classification number: G05F3/265 ,  G05F3/222

Abstract: A current generator stage for integrated analog circuits includes a current source connected between a supply voltage and a ground terminal. A current mirror is operationally connected to the current source to generate an output current. A bias circuit is operationally connected to the current source to perform switching of the current source from a first operating mode to a second operating mode. The bias circuit includes an energy storage circuit which, in a first circuit configuration, supplies to the current source a first predetermined voltage when the current source is in the first operating mode. The energy storage circuit in a second circuit configuration is a combination of first and second reactances to supply to the current source a second predetermined voltage when the current source is in the second operating mode.

Abstract translation: 用于集成模拟电路的电流发生器级包括连接在电源电压和接地端子之间的电流源。 电流镜可操作地连接到电流源以产生输出电流。 偏置电路可操作地连接到电流源，以将电流源从第一操作模式切换到第二操作模式。 偏置电路包括能量存储电路，其在第一电路配置中，当电流源处于第一操作模式时，向电流源提供第一预定电压。 第二电路配置中的能量存储电路是第一和第二电抗的组合，以在电流源处于第二操作模式时向电流源提供第二预定电压。

公开(公告)号：US5796302A

公开(公告)日：1998-08-18

申请号：US607601

申请日：1996-02-27

Applicant: Marco Masini ,  Stefania Boiocchi ,  Edoardo Botti

Inventor： Marco Masini ,  Stefania Boiocchi ,  Edoardo Botti

IPC: H03F1/08 ,  H03F3/217 ,  H03K7/08 ,  H03F3/38

CPC classification number: H03F1/083 ,  H03F3/217 ,  H03K7/08

Abstract: A single-pole negative feedback D-class amplifier having first and second input terminals for coupling to a signal source and an output terminal through which it transfers pulse modulated signals to a demodulating filter. A first resistor is feedback connected between the output terminal and an input circuit node connected to the second input terminal. A second resistor is connected between the input circuit node and the second input terminal. A capacitor is connected between the input circuit node and the first input terminal.

Abstract translation: 具有用于耦合到信号源的第一和第二输入端的单极负反馈D级放大器和将脉冲调制信号传送到解调滤波器的输出端。 第一电阻器反馈连接在输出端子和连接到第二输入端子的输入电路节点之间。 第二电阻连接在输入电路节点和第二输入端之间。 电容器连接在输入电路节点和第一输入端子之间。

公开(公告)号：US5793699A

公开(公告)日：1998-08-11

申请号：US811386

申请日：1997-03-04

Applicant: Luigi Pascucci

Inventor： Luigi Pascucci

IPC: G11C8/18 ,  G11C8/00

CPC classification number: G11C8/18

Abstract: A circuit for generating and resetting timing signals used for reading a memory device, includes first detecting circuit means for detecting a state transition of address digital signals of the memory device, the detecting means being suitable of generating a start digital signal of a read operation represented by a digital pulse of a prescribed duration upon a state transition of at least one of said address signals, second circuit means activated by said start signal for generating a timing signal for the read operation of the memory device, and third circuit means driven by said start digital signal for generating resetting signals for said timing signals, and fourth circuit means for detecting than said start signal has a duration shorter that said prescribed duration and for determining a consequent extension of the duration of said start signal sufficient to assure the generation of said resetting signals.

Abstract translation: 一种用于产生和复位用于读取存储器件的定时信号的电路，包括用于检测存储器件的地址数字信号的状态转换的第一检测电路装置，该检测装置适于产生表示的读取操作的起始数字信号 通过在至少一个所述地址信号的状态转换时的规定持续时间的数字脉冲，由所述起始信号激活的第二电路装置，用于产生用于存储器件的读取操作的定时信号;以及第三电路装置， 启动用于产生用于所述定时信号的复位信号的数字信号，以及用于比所述起始信号检测的第四电路装置具有比所述规定持续时间短的持续时间，并且用于确定所述起始信号的持续时间的延续足以确保产生所述 复位信号。