-
公开(公告)号：US09100008B2
公开(公告)日：2015-08-04
申请号：US13526092
申请日：2012-06-18
Applicant: Benedict C. K. Choy , James T. Walker , Ming-Yuan Yeh
Inventor： Benedict C. K. Choy , James T. Walker , Ming-Yuan Yeh
CPC classification number: H03K17/063 , H03K17/163
Abstract: Systems and methods are disclosed for operating a highly linearized resistance for a switch through use of a bootstrapped features. In one exemplary implementation, there is provided a method and system that implements a method for operating a circuit configured to provide a highly linearized resistance including receiving a signal via a bootstrapped switch, coupling the received signal to a gate if the received signal is high, receiving a signal via a switch control input coupled to a high impedance element. Moreover, the method includes coupling the high impedance element to the gate and turning off the switch via a gate turn off when the gate turn off pulls the gate low.
Abstract translation: 公开了用于通过使用自举特征来操作用于开关的高度线性化电阻的系统和方法。 在一个示例性实施方式中，提供了一种方法和系统，其实现用于操作被配置为提供高度线性化电阻的电路的方法，所述电路包括经由自举交换器接收信号，如果接收信号为高，则将接收信号耦合到门， 通过耦合到高阻抗元件的开关控制输入来接收信号。 此外，该方法包括将高阻抗元件耦合到栅极并且当栅极关断将栅极拉低时通过栅极截止来关断开关。
-
公开(公告)号：US20110255346A1
公开(公告)日：2011-10-20
申请号：US13172599
申请日：2011-06-29
Applicant: Hieu Van Tran , Sang T. Nguyen , Anh Ly , Hung Q. Nguyen
Inventor： Hieu Van Tran , Sang T. Nguyen , Anh Ly , Hung Q. Nguyen
Abstract: Various circuits include MOS transistors that have a bulk voltage terminal for receiving a bulk voltage that is different from a supply voltage and ground. The bulk voltage may be selectively set so that some MOS transistors have a bulk voltage set to the supply voltage or ground and other MOS transistors have a bulk voltage that is different. The bulk voltage may be set to forward or reverse bias pn junctions in the MOS transistor. The various circuits include comparators, operational amplifiers, sensing circuits, decoding circuits and the other circuits. The circuits may be included in a memory system.
Abstract translation: 各种电路包括具有用于接收不同于电源电压和接地的体电压的体电压端子的MOS晶体管。 可以选择性地设置体电压，使得一些MOS晶体管具有设置为电源电压或地的体电压，并且其它MOS晶体管具有不同的体电压。 体电压可以被设置为MOS晶体管中的正向或反向偏置pn结。 各种电路包括比较器，运算放大器，感测电路，解码电路和其它电路。 电路可以包括在存储器系统中。
-
公开(公告)号：US07728679B2
公开(公告)日：2010-06-01
申请号：US12171277
申请日：2008-07-10
Applicant: Stanley Wang , Bendik Kleveland , Thomas H. Lee
Inventor： Stanley Wang , Bendik Kleveland , Thomas H. Lee
IPC: H03L1/00
CPC classification number: H03L7/099
Abstract: A calibration circuit (20, 50) and method (60) for calibrating the bias current of a VCO (10, 40) to minimize phase noise. The calibration circuit (20, 50) monitors the average voltage at the common-mode node of the VCO (10, 40) while varying the bias current over a predetermined range. The calibration circuit (20, 50) identifies the bias current associated with the minimum average common-mode voltage and utilizes this bias current for calibrating the biasing transistor of the VCO (10, 40).
Abstract translation: 一种用于校准VCO（10,40）的偏置电流以最小化相位噪声的校准电路（20,50）和方法（60）。 校准电路（20,50）在偏置电流超过预定范围的同时监视VCO（10,40）的共模节点处的平均电压。 校准电路（20,50）识别与最小平均共模电压相关联的偏置电流，并利用该偏置电流来校准VCO（10,40）的偏置晶体管。
-
公开(公告)号：US07209030B2
公开(公告)日：2007-04-24
申请号：US11079787
申请日：2005-03-14
Applicant: James B. Nolan , Thomas Youbok Lee , Steve Vernier , Alan Lamphier
Inventor： James B. Nolan , Thomas Youbok Lee , Steve Vernier , Alan Lamphier
CPC classification number: B60R25/24 , B60R25/406 , G07C9/00309 , G07C2009/00769
Abstract: A remote keyless entry (RKE) transponder has a noise alarm timer having a time interval used for determining whether a received signal meets a predefined condition within a time interval. If the received signal meets the predefined condition within the time interval, the noise alarm timer is disabled and the RKE transponder circuits are enabled so that normal operation in processing the desired signal commences. If the received signal does not meet the predefined condition within the time interval the noise alarm timer issues an alert signal, whereby appropriate action may be taken such as adjusting the channel input sensitivity, disabling a channel, or placing the RKE transponder into a sleep mode in order to reduce the power consumption caused by undesired input signals. A smart wake-up filter determines whether or not the input signal meets the predefined condition within the time interval.
Abstract translation: 远程无钥匙进入（RKE）转发器具有噪声报警定时器，其具有用于确定接收到的信号是否在时间间隔内满足预定义条件的时间间隔。 如果接收到的信号在时间间隔内满足预定义的条件，噪声警报定时器被禁止，并且RKE应答器电路被使能，使得处理所需信号的正常操作开始。 如果接收到的信号在时间间隔内不满足预定义的条件，则噪声报警定时器发出报警信号，由此可以采取适当的动作，例如调整通道输入灵敏度，禁用通道或将RKE应答器置于睡眠模式 以减少由不期望的输入信号引起的功耗。 智能唤醒滤波器确定输入信号是否在时间间隔内满足预定义的条件。
-
公开(公告)号：US07206924B2
公开(公告)日：2007-04-17
申请号：US10751210
申请日：2003-12-31
Applicant: Edward Brian Boles , Rodney Drake , Darrel Johansen , Sumit Mitra , Joseph Triece , Randy Yach
Inventor： Edward Brian Boles , Rodney Drake , Darrel Johansen , Sumit Mitra , Joseph Triece , Randy Yach
IPC: G06F12/08
CPC classification number: G06F9/30192 , G06F9/30032 , G06F9/3004 , G06F9/30101 , G06F9/3012 , G06F9/3013 , G06F9/30145 , G06F9/30149 , G06F9/30167 , G06F9/321 , G06F9/325
Abstract: A microcontroller apparatus is provided with an instruction set for manipulating the behavior of the microcontroller. The apparatus and system is provided that enables a linearized address space that makes modular emulation possible. Direct or indirect addressing is possible through register files or data memory. Special function registers, including the Program Counter (PC) and Working Register (W), are mapped in the data memory. An orthogonal (symmetrical) instruction set makes possible any operation on any register using any addressing mode. Consequently, two file registers to be used in some two operand instructions. This allows data to be moved directly between two registers without going through the W register. Thus increasing performances and decreasing program memory usage.
Abstract translation: 微控制器装置设置有用于操纵微控制器的行为的指令集。 提供了使得能够实现模块化仿真的线性化地址空间的装置和系统。 可以通过寄存器文件或数据存储器进行直接或间接寻址。 特殊功能寄存器，包括程序计数器（PC）和工作寄存器（W），映射到数据存储器中。 正交（对称）指令集可以使用任何寻址模式对任何寄存器进行任何操作。 因此，在两个操作数指令中要使用两个文件寄存器。 这允许在两个寄存器之间直接移动数据，而不经过W寄存器。 从而增加性能并减少程序内存的使用。
-
Patent Agency Ranking
公开(公告)号：US6166650A
公开(公告)日：2000-12-26
申请号：US868131
申请日：1997-06-03
Applicant: Frederick Bruwer
Inventor： Frederick Bruwer
CPC classification number: G07C9/00182 , G07C9/00817 , G07C9/00857 , G07C2009/0023 , G07C2009/00253 , G07C2009/00769 , G07C2009/00928 , G07C2209/06 , H04L9/0869 , H04L2209/34 , H04L2209/80 , H04L2209/84
Abstract: A method and system for the remote control of devices having a secure self learn capability. The system includes an encoder and a decoder, the encoder encoding variable information including a user key using a non-linear algorithm to produce an encoded value transmitted to the decoder, the decoder decoding the value using the same algorithm. In a learning mode a new encoder is to be added to the system. The new encoder produces an encoded value using a key generation seed. The decoder, upon receiving the encoded key generation seed, produces a decoding key based upon the decoded key generation seed. The decoding key is stored in the decoder memory allowing valid recognition of the new encoder in a secure manner.
Abstract translation: 一种用于远程控制具有安全自学能力的装置的方法和系统。 该系统包括编码器和解码器，编码器编码包括使用非线性算法的用户密钥的变量信息以产生传输到解码器的编码值，解码器使用相同的算法解码该值。 在学习模式下，将新的编码器添加到系统中。 新编码器使用密钥生成种子生成编码值。 解码器在接收到编码的密钥生成种子后，基于解码的密钥生成种子产生解码密钥。 解码密钥存储在解码器存储器中，从而以安全的方式有效地识别新的编码器。
-
公开(公告)号：US5014191A
公开(公告)日：1991-05-07
申请号：US189189
申请日：1988-05-02
Applicant: Ajay J. Padgaonkar , Sumit K. Mitra
Inventor： Ajay J. Padgaonkar , Sumit K. Mitra
IPC: G06F21/00
CPC classification number: G06F21/79 , G06F21/74 , G06F2221/2105
Abstract: The processor executes programs from an internal EEPROM or from an external source. The EEPROM can be read either by a special operating (test) mode of the processor or by an instruction executing under normal operating mode from the EEPROM or from an external source. Similarly, the EEPROM can be programmed (written) either by a special operating mode or by under a normal operating mode instruction. The read and write circuits for the EEPROM are controlled to provide two levels of security against piracy of programmed information. In the first level, access is prevented for the read and write test modes and also for the read and write normal operating instructions if the instructions originate from an external source. In the second level, program execution from external source is also disabled.
Abstract translation: 处理器从内部EEPROM或外部源执行程序。 EEPROM可以通过处理器的特殊操作（测试）模式或通过从EEPROM或外部源在正常工作模式下执行的指令来读取。 类似地，EEPROM可以通过特殊操作模式或正常工作模式指令进行编程（写入）。 控制EEPROM的读和写电路，以提供两级安全性，防止编程信息的盗版。 在第一级中，如果指令源于外部源，则可以访问读取和写入测试模式以及读取和写入正常操作指令。 在第二级，外部源程序执行也被禁用。
-
公开(公告)号：US12175116B2
公开(公告)日：2024-12-24
申请号：US17669995
申请日：2022-02-11
Applicant: Microchip Technology Inc.
Inventor： Christopher I. W. Norrie
IPC: G06F3/06
Abstract: In one implementation a vector processor gather/scatter apparatus comprises a plurality of vector ports, and a random access memory, where the plurality of vector ports are in communication with the random access memory, and where one or more of the plurality of vector ports uses one or more of an address register and one or more of a stride register in communication with the random access memory to allow the gather/scatter of random access memory contents.
-
公开(公告)号：US11811568B2
公开(公告)日：2023-11-07
申请号：US17818224
申请日：2022-08-08
Applicant: Microchip Technology Incorporated
Inventor： Johannes G. Ransijn
CPC classification number: H04L25/03878 , H04B1/16 , H04B3/14 , H04L25/03057 , H04L25/08 , H04L27/01
Abstract: Front-end circuitry for a data receiver and related systems, methods, and devices are disclosed. The front-end circuitry includes a passive equalizer, which includes a signal input, an equalizer output including a first equalizer output and a second equalizer output, a first signal path, and a second signal path. The first signal path is between the signal input and the first equalizer output. The first signal path has a first frequency response. The second signal path is between the signal input and the second equalizer output. The second signal path has a second frequency response. The second frequency response exhibits substantially inverse behavior to that of the first frequency response. An amplifier circuit is configured to combine a first equalizer output signal from the first equalizer output with a second equalizer output signal from the second equalizer output to obtain an equalized output signal.
-
公开(公告)号：US11526343B2
公开(公告)日：2022-12-13
申请号：US16577251
申请日：2019-09-20
Applicant: Microchip Technology Inc.
Inventor： Nilesh Rajbharti , Mark Ennamorato
Abstract: A system and method for improved evaluation of semiconductor hardware is provided. The system comprises a firmware repository server, which firmware repository server comprises a plurality of firmware packages for the one or more evaluation hardware boards. The firmware repository server is further configured to: receive a firmware request for a user evaluation hardware board from a first of the client devices, search the plurality of firmware packages for compatible firmware packages for the user evaluation hardware board, generate a catalog of the compatible firmware packages for the user evaluation hardware board, transmit the catalog to the first client device, receive a request for a user selected firmware package from the catalog of compatible firmware packages, and to transmit firmware of the user selected firmware package to the client device for installation on the user evaluation hardware board.
-
-
-
-
-
-
-
-
-
Search Results
185
records
(took 0.026 seconds)
