公开(公告)号：US06713406B1

公开(公告)日：2004-03-30

申请号：US09809833

申请日：2001-03-19

申请人： Chu-Yun Fu ,  Kuo-Chyuan Tzeng

发明人： Chu-Yun Fu ,  Kuo-Chyuan Tzeng

IPC分类号： H01L21302

CPC分类号： H01L21/02274 ,  H01L21/02129 ,  H01L21/02164 ,  H01L21/3105 ,  H01L21/31612 ,  H01L21/31625

摘要： Improved processes for depositing dielectric layers by HDP (High Density Plasma) CVD (Chemical Vapor Deposition) are described. One method controls the RF power applied to the side source RF power to be less than about 2500 Watts during dielectric deposition. A second method controls the thickness of the HDP-CVD deposited dielectric layer to be less than between about 2000 and 3000 Angstroms. These methods of HDP-CVD deposition of dielectric layers result in elimination or suppression of plasma induced damage to MOSFET devices and improved gate oxide integrity of MOSFET devices following deposition of dielectric layers by HDP-CVD.

摘要翻译： 描述了通过HDP（高密度等离子体）CVD（化学气相沉积）沉积电介质层的改进方法。 在电介质沉积期间，一种方法控制施加到侧源RF功率的RF功率小于约2500瓦。 第二种方法控制HDP-CVD沉积介电层的厚度小于约2000和3000埃之间。 介电层的HDP-CVD沉积的这些方法导致在通过HDP-CVD沉积介电层之后消除或抑制对MOSFET器件的等离子体诱导的损坏并改善MOSFET器件的栅极氧化物完整性。

公开(公告)号：US06479385B1

公开(公告)日：2002-11-12

申请号：US09583397

申请日：2000-05-31

申请人： Syun-Ming Jang ,  Chu-Yun Fu

发明人： Syun-Ming Jang ,  Chu-Yun Fu

IPC分类号： H01L21302

CPC分类号： H01L21/02238 ,  H01L21/02129 ,  H01L21/02164 ,  H01L21/022 ,  H01L21/02255 ,  H01L21/02271 ,  H01L21/02274 ,  H01L21/31612 ,  H01L21/31625 ,  H01L21/76801 ,  H01L21/76837

摘要： A process for forming a composite, interlevel dielectric, (ILD), layer, for MOSFET devices, has been developed. The composite ILD layer is comprised with an underlying, undoped silicon glass layer, providing the material needed to fill the narrow spaces between polysilicon gate structures of the MOSFET devices. A P2O5 doped, insulator layer, is next formed on the underlying, undoped silicon glass layer, to provide a mobile ion gettering property. An overlying, undoped silicon glass layer is then deposited and subjected to a chemical mechanical polishing procedure, resulting in the desired planar top surface topography, for the composite ILD layer.

摘要翻译： 已经开发了用于形成MOSFET器件的复合层间电介质（ILD）层的工艺。 复合ILD层包含底层的未掺杂的硅玻璃层，提供填充MOSFET器件的多晶硅栅极结构之间的狭窄空间所需的材料。 随后在下面未掺杂的硅玻璃层上形成P2O5掺杂的绝缘体层，以提供移动离子吸杂性质。 然后沉积覆盖的未掺杂的硅玻璃层，并进行化学机械抛光程序，得到复合ILD层所需的平面顶表面形貌。

公开(公告)号：US06316348B1

公开(公告)日：2001-11-13

申请号：US09838627

申请日：2001-04-20

申请人： Chu Yun Fu ,  Chia Shiung Tsai ,  Syun-Ming Jang

发明人： Chu Yun Fu ,  Chia Shiung Tsai ,  Syun-Ming Jang

IPC分类号： H01L214763

CPC分类号： H01L21/76829 ,  H01L21/0276 ,  H01L21/0332 ,  H01L21/0337 ,  H01L21/31116 ,  H01L21/3144 ,  H01L21/3145 ,  H01L21/76801 ,  H01L21/7681 ,  H01L21/76813

摘要： The present invention provides an anti-reflective Si-Rich Silicon oxynitride (SiON) etch barrier layer and two compatible oxide etch processes. The Si-Rich Silicon oxynitride (SiON) etch barrier layer can be used as a hard mask in a dual damascene structure and as a hard mask for over a polysilicone gate. The invention has the following key elements: 1) Si rich Silicon oxynitride (SiON) ARC layer, 2) Special Silicon oxide Etch process that has a high selectivity of Si-Rich SiON to silicon oxide or SiN; 3) Special Si Rich SiON spacer process for a self aligned contact (SAC). A dual damascene structure is formed by depositing a first dielectric layer. A novel anti-reflective Si-Rich Silicon oxynitride (SiON) etch barrier layer is deposited on top of the first dielectric layer. A first opening is etched in the first insulating layer. A second dielectric layer is deposited on the anti-reflective Si-Rich Silicon oxynitride (SiON) etch barrier layer. A second dual damascene opening is etched into the dielectric layers. The anti-reflective Si-Rich Silicon oxynnitride (SiON) etch barrier layer can also serve as an ARC layer during these operations to reduce the amount of reflectance from conductive region to reduce distortion of the photoresist pattern.

摘要翻译： 本发明提供了抗反射富Si硅氮化硅（SiON）蚀刻阻挡层和两种相容的氧化物蚀刻工艺。 Si富氧硅氮化物（SiON）蚀刻阻挡层可用作双镶嵌结构中的硬掩模，并且可用作多晶硅栅极上的硬掩模。 本发明具有以下关键要素：1）富硅氧氮化硅（SiON）ARC层，2）具有Si富Si硅对硅氧化物或SiN的高选择性的特殊氧化硅蚀刻工艺; 3）用于自对准接触（SAC）的特殊Si Rich SiON隔离工艺。通过沉积第一介电层形成双镶嵌结构。 在第一介电层的顶部沉积有新的抗反射硅富氮硅氮化硅（SiON）蚀刻阻挡层。 在第一绝缘层中蚀刻第一开口。 第二电介质层沉积在抗反射富Si硅氮化硅（SiON）蚀刻阻挡层上。 第二个双镶嵌开口被蚀刻到电介质层中。 在这些操作期间，抗反射Si富硅氧氮化物（SiON）蚀刻阻挡层也可以用作ARC层，以减少来自导电区域的反射率，以减少光致抗蚀剂图案的变形。

公开(公告)号：US06245682B1

公开(公告)日：2001-06-12

申请号：US09266374

申请日：1999-03-11

申请人： Chu-Yun Fu ,  Syun-Ming Jang

发明人： Chu-Yun Fu ,  Syun-Ming Jang

IPC分类号： H01L21311

CPC分类号： H01L21/32139 ,  H01L21/28123 ,  H01L21/31111 ,  H01L21/3145 ,  Y10S438/952

摘要： This invention relates to the fabrication of integrated circuit devices and more particularly to a method for forming and then later removing a silicon oxynitride, SiON, anti-reflection coating (ARC) over a semiconductor substrate, for the purpose of enhancing the resolution of photolithographically defined sub-micron polysilicon gates. The problem addressed by this invention is that the SiON ARC must first be used to reduce optical reflection from a blanket polysilicon surface, during the photolithography exposure step that defines the sub-micron polysilicon gate features, and then the ARC must be removed by a wet etch process that will not chemically attack the gate oxide under the polysilicon gate features or any exposed polysilicon surfaces. This is accomplished with a fabrication method that uses hot phosphoric acid (H3PO4) to preferentially etch the SiON ARC, relative to the thermal gate oxide, while also using thin thermal oxide layers to protect the polysilicon gate surfaces from being severely attacked by the hot H3PO4. This new method also features the ability to tailor the combination of the composition and thickness of the SiON layer and the thickness of the underlying protective thin thermal oxide layer, in order to minimize the undesired high optical reflectivity of the underlying polysilicon surface.

摘要翻译： 本发明涉及集成电路器件的制造，更具体地说，涉及一种用于在半导体衬底上形成并随后去除氧氮化硅SiON，抗反射涂层（ARC）的方法，用于增强光刻定义的分辨率 亚微米多晶硅门。 本发明解决的问题是，在限定亚微米多晶硅栅极特征的光刻曝光步骤期间，必须首先使用SiON ARC来减少来自覆盖多晶硅表面的光学反射，然后必须通过湿法去除ARC 不会在多晶硅栅极特征或任何暴露的多晶硅表面下化学侵蚀栅极氧化物的蚀刻工艺。 这是通过使用热磷酸（H 3 PO 4）相对于热栅氧化物优先蚀刻SiON ARC的制造方法实现的，同时还使用薄的热氧化物层来保护多晶硅栅极表面免受热H3PO4的严重攻击 。 这种新方法还具有能够定制SiON层的组成和厚度以及下面的保护性薄热氧化物层的厚度的组合，以便使底层多晶硅表面的不期望的高光学反射率最小化。

公开(公告)号：US06245669B1

公开(公告)日：2001-06-12

申请号：US09245564

申请日：1999-02-05

申请人： Chu Yun Fu ,  Chia Shiung Tsai ,  Syun-Ming Jang

发明人： Chu Yun Fu ,  Chia Shiung Tsai ,  Syun-Ming Jang

IPC分类号： H01L214763

CPC分类号： H01L21/76829 ,  H01L21/0276 ,  H01L21/0332 ,  H01L21/0337 ,  H01L21/31116 ,  H01L21/3144 ,  H01L21/3145 ,  H01L21/76801 ,  H01L21/7681 ,  H01L21/76813

摘要： The present invention provides an anti-reflective Si-Rich Silicon oxynitride (SiON) etch barrier layer and two compatible oxide etch processes. The Si-Rich Silicon oxynitride (SiON) etch barrier layer can be used as a hard mask in a dual damascene structure and as a hard mask for over a polysilicon gate. The invention has the following key elements: 1) Si rich Silicon oxynitride (SiON) ARC layer, 2) Special Silicon oxide Etch process that has a high selectivity of Si-Rich SiON to silicon oxide or SiN; 3) Special Si Rich SiON spacer process for a self aligned contact (SAC). A dual damascene structure is formed by depositing a first dielectric layer. A novel anti-reflective Si-Rich Silicon oxynitride (SiON) etch barrier layer is deposited on top of the first dielectric layer. A first opening is etched in the first insulating layer. A second dielectric layer is deposited on the anti-reflective Si-Rich Silicon oxynitride (SiON) etch barrier layer. A second dual damascene opening is etched into the dielectric layers. The anti-reflective Si-Rich Silicon oxynitride (SiON) etch barrier layer can also serve as an ARC layer during these operations to reduce the amount of reflectance from conductive region to reduce distortion of the photoresist pattern.

摘要翻译： 本发明提供了抗反射富Si硅氮化硅（SiON）蚀刻阻挡层和两种相容的氧化物蚀刻工艺。 Si富氧硅氮化物（SiON）蚀刻阻挡层可用作双镶嵌结构中的硬掩模，并可用作多晶硅栅极上的硬掩模。 本发明具有以下关键要素：1）富硅氧氮化硅（SiON）ARC层，2）具有Si富Si硅对硅氧化物或SiN的高选择性的特殊氧化硅蚀刻工艺; 3）用于自对准接触（SAC）的特殊Si Rich SiON隔离工艺。通过沉积第一介电层形成双镶嵌结构。 在第一介电层的顶部沉积有新的抗反射硅富氮硅氮化硅（SiON）蚀刻阻挡层。 在第一绝缘层中蚀刻第一开口。 第二电介质层沉积在抗反射富Si硅氮化硅（SiON）蚀刻阻挡层上。 第二个双镶嵌开口被蚀刻到电介质层中。 在这些操作期间，抗反射硅富氮硅氮化物（SiON）蚀刻阻挡层也可以用作ARC层，以减少来自导电区域的反射率，以减少光致抗蚀剂图案的失真。

公开(公告)号：US06207483B1

公开(公告)日：2001-03-27

申请号：US09527183

申请日：2000-03-17

申请人： Chu-Yun Fu ,  Chung-Long Chang ,  Syun-Ming Jang ,  Shwangming Jeng

发明人： Chu-Yun Fu ,  Chung-Long Chang ,  Syun-Ming Jang ,  Shwangming Jeng

IPC分类号： H01L218238

CPC分类号： H01L21/823828 ,  H01L21/28035 ,  H01L21/32115

摘要： There is provided a method for smoothing the surface of undoped polysilicon regions of a CMOS structure, primarily gate regions. A direct HPD-CVD argon sputter is used improve the surface roughness by a factor of more than 50%. The argon plasma sputter may be used either alone or in conjunction with a thin capping layer of oxide, nitride or oxynitride. The devices manufactured using the process exhibit excellent electrical characteristics and improved reliability compared to devices made using conventional manufacturing processes.

摘要翻译： 提供了一种用于平滑CMOS结构的未掺杂多晶硅区域的表面的方法，主要是栅极区域。 使用直接HPD-CVD氩溅射将表面粗糙度提高了50％以上。 氩等离子体溅射可以单独使用或与氧化物，氮化物或氮氧化物的薄覆盖层结合使用。 与使用常规制造工艺制造的器件相比，使用该工艺制造的器件表现出优异的电气特性和改进的可靠性。

公开(公告)号：US6090714A

公开(公告)日：2000-07-18

申请号：US177189

申请日：1998-10-23

申请人： Syun-Ming Jang ,  Chu-Yun Fu

发明人： Syun-Ming Jang ,  Chu-Yun Fu

IPC分类号： H01L21/3105 ,  H01L21/316 ,  H01L21/762 ,  H01L21/302

CPC分类号： H01L21/76229 ,  H01L21/31055 ,  H01L21/31608

摘要： A method for forming a planarized trench fill layer within a trench within a substrate. There is first provided a substrate having a trench formed therein. There is then formed over the substrate and at least partially filling the trench a first trench fill layer formed employing a high density plasma chemical vapor deposition (HDP-CVD) method. There is then formed upon the first trench fill layer a second trench fill layer formed employing a subatmospheric pressure thermal chemical vapor deposition (SACVD) method employing ozone as an oxidant source material and tetraethylorthosilicate (TEOS) as a silicon source material. Finally, there is then planarized by employing a chemical mechanical polish (CMP) planarizing method the second trench fill layer and the first trench fill layer to form a patterned planarized trench fill layer within the trench. When employing the method, the first trench fill layer is formed to a first thickness and the second trench fill layer is formed to a second thickness, where the first thickness and the second thickness are chosen such that there is attenuated erosion of the substrate when forming the patterned planarized trench fill layer within the trench while employing the chemical mechanical polish (CMP) planarizing method. The method is particularly useful for forming patterned planarized trench fill dielectric layers within isolation trenches within semiconductor substrates employed within semiconductor integrated circuit microelectronics fabrications.

摘要翻译： 一种用于在衬底内的沟槽内形成平坦化的沟槽填充层的方法。 首先提供其中形成有沟槽的衬底。 然后在衬底上形成并且至少部分地填充沟槽，使用高密度等离子体化学气相沉积（HDP-CVD）方法形成的第一沟槽填充层。 然后在第一沟槽填充层上形成第二沟槽填充层，该第二沟槽填充层采用使用臭氧作为氧化剂源材料和四乙基原硅酸盐（TEOS）作为硅源材料的低于大气压的热化学气相沉积（SACVD）方法。 最后，然后通过采用化学机械抛光（CMP）平面化方法平面化第二沟槽填充层和第一沟槽填充层，以在沟槽内形成图案化的平坦化沟槽填充层。 当采用该方法时，第一沟槽填充层被形成为第一厚度，并且第二沟槽填充层被形成为第二厚度，其中第一厚度和第二厚度被选择为使得当形成时基板受到衰减的侵蚀 在使用化学机械抛光（CMP）平面化方法的同时，在沟槽内形成图案化的平坦化沟槽填充层。 该方法对于在半导体集成电路微电子器件制造中使用的半导体衬底内的隔离沟槽内形成图案化的平坦化沟槽填充电介质层特别有用。

公开(公告)号：US6037018A

公开(公告)日：2000-03-14

申请号：US108866

申请日：1998-07-01

申请人： Syun-Ming Jang ,  Chu-Yun Fu ,  Chen-Hua Douglas Yu

发明人： Syun-Ming Jang ,  Chu-Yun Fu ,  Chen-Hua Douglas Yu

IPC分类号： C23C16/40 ,  H01L21/762 ,  B05D3/06 ,  H01L21/76

CPC分类号： H01L21/76232 ,  C23C16/402

摘要： A method for filling shallow trenches 28 with a HDPCVD oxide 50. The invention has two liners: (a) a thermal oxide liner 36 and (b) an overlying conformal O.sub.3 -TEOS protective liner 40. The O.sub.3 -TEOS protective liner 40 prevents the HDPCVD oxide 50 from sputter damaging the trench sidewalls and the masking layer 24. The O.sub.3 -TEOS layer has novel process temperature (400 to 560.degree. C.) and low pressure (40 to 80 torr) that allows the O.sub.3 -TEOS layer to deposit uniformly over thermal oxide liner 36. The method begins by forming pad oxide layer 20 and a barrier layer 24 over a substrate. A trench 28 is formed in the substrate 10 through the pad oxide layer 20 and the barrier layer 24. A thermal oxide liner 36 and a protective O.sub.3 -TEOS liner layer 40 are formed over the walls of the trench 28 and over the barrier layer 24. Lastly, a high density plasma chemical vapor deposition (HDPCVD) oxide layer 50 is formed over the protective liner layer 40 filling the trench 28.

摘要翻译： 用HDPCVD氧化物50填充浅沟槽28的方法。本发明具有两个衬垫：（a）热氧化物衬垫36和（b）上覆的共形O3-TEOS保护衬垫40.O3-TEOS保护衬垫40防止 HDPCVD氧化物50从溅射破坏沟槽侧壁和掩模层24.O3-TEOS层具有新的工艺温度（400至560℃）和低压（40至80托），允许O 3 -TEOS层沉积 该方法开始于在衬底上形成衬垫氧化物层20和阻挡层24。 沟槽28通过衬垫氧化物层20和阻挡层24形成在衬底10中。热氧化物衬里36和保护性O 3 -TEOS衬里层40形成在沟槽28的壁上并且在阻挡层24上方 最后，在填充沟槽28的保护衬垫层40之上形成高密度等离子体化学气相沉积（HDPCVD）氧化物层50。

公开(公告)号：US20130171803A1

公开(公告)日：2013-07-04

申请号：US13775907

申请日：2013-02-25

申请人： Tze-Liang LEE ,  Pei-Ren JENG ,  Chu-Yun FU ,  Chyi Shyuan CHERN ,  Jui-Hei HUANG ,  Chih-Tang PENG ,  Hao-Ming LIEN

发明人： Tze-Liang LEE ,  Pei-Ren JENG ,  Chu-Yun FU ,  Chyi Shyuan CHERN ,  Jui-Hei HUANG ,  Chih-Tang PENG ,  Hao-Ming LIEN

IPC分类号： H01L21/762

CPC分类号： H01L21/76224 ,  H01L21/76232

摘要： A method of fabricating an isolation structure including forming a trench in a top surface of a substrate and partially filling the trench with a first oxide, wherein the first oxide is a pure oxide. Partially filling the trench includes forming a liner layer in the trench and forming the first oxide over the liner layer using silane and oxygen precursors at a pressure less than 10 milliTorr (mTorr) and a temperature ranging from about 500° C. to about 1000° C. The method further includes producing a solid reaction product in a top portion of the first oxide. The method further includes sublimating the solid reaction product by heating the substrate in a chamber at a temperature from 100° C. to 200° C. and removing the sublimated solid reaction product by flowing a carrier gas over the substrate. The method further includes filling the trench with a second oxide.

摘要翻译： 一种制造隔离结构的方法，包括在衬底的顶表面中形成沟槽并用第一氧化物部分地填充沟槽，其中第一氧化物是纯氧化物。 部分地填充沟槽包括在沟槽中形成衬层，并且在低于10毫托（mTorr）的压力和约500℃至约1000℃的温度下使用硅烷和氧前体在衬层上形成第一氧化物 该方法还包括在第一氧化物的顶部产生固体反应产物。 该方法还包括通过在室内在100℃至200℃的温度下加热基底来升华固体反应产物，并通过使载气流过基底而除去升华的固体反应产物。 该方法还包括用第二氧化物填充沟槽。

公开(公告)号：US20120091538A1

公开(公告)日：2012-04-19

申请号：US12903712

申请日：2010-10-13

申请人： Hung-Ta LIN ,  Chu-Yun FU ,  Shin-Yeh HUANG ,  Shu-Tine YANG ,  Hung-Ming CHEN

发明人： Hung-Ta LIN ,  Chu-Yun FU ,  Shin-Yeh HUANG ,  Shu-Tine YANG ,  Hung-Ming CHEN

IPC分类号： H01L29/78 ,  H01L21/311

CPC分类号： H01L27/0886 ,  H01L21/02293 ,  H01L29/165 ,  H01L29/66636 ,  H01L29/66795 ,  H01L29/7842 ,  H01L29/7848 ,  H01L29/785 ,  H01L29/7855

摘要： The disclosure relates to a fin field effect transistor (FinFET). An exemplary structure for a FinFET comprises a substrate comprising a top surface; a first insulation region and a second insulation region over the substrate top surface comprising tapered top surfaces; a fin of the substrate extending above the substrate top surface between the first and second insulation regions, wherein the fin comprises a recessed portion having a top surface lower than the tapered top surfaces of the first and second insulation regions, wherein the fin comprises a non-recessed portion having a top surface higher than the tapered top surfaces; and a gate stack over the non-recessed portion of the fin.

摘要翻译： 本发明涉及鳍状场效应晶体管（FinFET）。 FinFET的示例性结构包括：包括顶表面的衬底; 第一绝缘区域和位于衬底顶表面上的第二绝缘区域，包括锥形顶表面; 在所述第一和第二绝缘区域之间延伸到所述衬底顶表面之上的所述衬底的翅片，其中所述鳍片包括具有比所述第一和第二绝缘区域的锥形顶表面低的顶表面的凹陷部分，其中所述鳍片包括非 加工部分具有高于锥形顶表面的顶表面; 以及在翅片的非凹陷部分上方的栅极堆叠。