公开(公告)号：US6037018A

公开(公告)日：2000-03-14

申请号：US108866

申请日：1998-07-01

申请人： Syun-Ming Jang ,  Chu-Yun Fu ,  Chen-Hua Douglas Yu

发明人： Syun-Ming Jang ,  Chu-Yun Fu ,  Chen-Hua Douglas Yu

IPC分类号： C23C16/40 ,  H01L21/762 ,  B05D3/06 ,  H01L21/76

CPC分类号： H01L21/76232 ,  C23C16/402

摘要： A method for filling shallow trenches 28 with a HDPCVD oxide 50. The invention has two liners: (a) a thermal oxide liner 36 and (b) an overlying conformal O.sub.3 -TEOS protective liner 40. The O.sub.3 -TEOS protective liner 40 prevents the HDPCVD oxide 50 from sputter damaging the trench sidewalls and the masking layer 24. The O.sub.3 -TEOS layer has novel process temperature (400 to 560.degree. C.) and low pressure (40 to 80 torr) that allows the O.sub.3 -TEOS layer to deposit uniformly over thermal oxide liner 36. The method begins by forming pad oxide layer 20 and a barrier layer 24 over a substrate. A trench 28 is formed in the substrate 10 through the pad oxide layer 20 and the barrier layer 24. A thermal oxide liner 36 and a protective O.sub.3 -TEOS liner layer 40 are formed over the walls of the trench 28 and over the barrier layer 24. Lastly, a high density plasma chemical vapor deposition (HDPCVD) oxide layer 50 is formed over the protective liner layer 40 filling the trench 28.

摘要翻译： 用HDPCVD氧化物50填充浅沟槽28的方法。本发明具有两个衬垫：（a）热氧化物衬垫36和（b）上覆的共形O3-TEOS保护衬垫40.O3-TEOS保护衬垫40防止 HDPCVD氧化物50从溅射破坏沟槽侧壁和掩模层24.O3-TEOS层具有新的工艺温度（400至560℃）和低压（40至80托），允许O 3 -TEOS层沉积 该方法开始于在衬底上形成衬垫氧化物层20和阻挡层24。 沟槽28通过衬垫氧化物层20和阻挡层24形成在衬底10中。热氧化物衬里36和保护性O 3 -TEOS衬里层40形成在沟槽28的壁上并且在阻挡层24上方 最后，在填充沟槽28的保护衬垫层40之上形成高密度等离子体化学气相沉积（HDPCVD）氧化物层50。

公开(公告)号：US6072237A

公开(公告)日：2000-06-06

申请号：US163382

申请日：1998-09-30

申请人： Syun-Ming Jang ,  Chen-Hua Douglas Yu

发明人： Syun-Ming Jang ,  Chen-Hua Douglas Yu

IPC分类号： H01L21/311 ,  H01L21/768 ,  H01L23/522 ,  H01L23/532 ,  H01K23/04

CPC分类号： H01L23/53223 ,  H01L21/31116 ,  H01L21/76802 ,  H01L21/76829 ,  H01L23/5226 ,  H01L23/5329 ,  H01L2924/0002

摘要： A method for forming a borderless, contact or via hole, has been developed, in which a thin silicon nitride layer is used as an etch stop to prevent attack of an underlying interlevel dielectric layer, during the opening of the borderless, contact or via hole, in an overlying, interlevel dielectric layer. The thin silicon nitride layer is the top layer of an interlevel dielectric composite layer, used between metal interconnect levels.

摘要翻译： 已经开发了用于形成无边界，接触或通孔的方法，其中使用薄氮化硅层作为蚀刻停止件，以防止在无边界接触或通孔的打开期间侵入下面的层间电介质层 在叠层的层间电介质层中。 薄的氮化硅层是在金属互连层之间使用的层间介质复合层的顶层。

公开(公告)号：US5955787A

公开(公告)日：1999-09-21

申请号：US892220

申请日：1997-07-14

申请人： Chen-Hua Douglas Yu ,  Syun-Ming Jang

发明人： Chen-Hua Douglas Yu ,  Syun-Ming Jang

IPC分类号： H01L21/768 ,  H01L23/532 ,  H01L21/441

CPC分类号： H01L21/76801 ,  H01L21/76832 ,  H01L21/76834 ,  H01L21/76837 ,  H01L23/5329 ,  H01L2924/0002

摘要： A defect free intermetal dielectric, IMD, and method of forming the defect free IMD are described. The IMD uses spacers formed by means of etchback of a layer of spin-on-glass, SOG. In order to use an oxide layer formed by means of plasma enhanced tetra-ethyl-ortho-silicate, PE-TEOS, as part of the IMD an oxide cap layer formed using plasma enhanced chemical vapor deposition, PE-CVD, is used to isolate the SOG spacers from the PE-TEOS formed oxide layer. By isolating the PE-TEOS formed oxide layer from the SOG spacers a reliable and defect free IMD is achieved.

摘要翻译： 描述了无缺陷的金属间电介质，IMD和形成无缺陷IMD的方法。 IMD使用通过回转一层旋涂玻璃（SOG）形成的间隔物。 为了使用通过等离子体增强的四乙基原硅酸盐形成的氧化物层，PE-TEOS作为IMD的一部分，使用等离子体增强化学气相沉积形成的氧化物覆盖层PE-CVD用于分离 来自PE-TEOS形成的氧化物层的SOG间隔物。 通过从SOG间隔隔离PE-TEOS形成的氧化物层，实现可靠且无缺陷的IMD。

公开(公告)号：US5674783A

公开(公告)日：1997-10-07

申请号：US625278

申请日：1996-04-01

申请人： Syun-Ming Jang ,  Chen-Hua Douglas Yu

发明人： Syun-Ming Jang ,  Chen-Hua Douglas Yu

IPC分类号： H01L21/3105 ,  H01L21/316

CPC分类号： H01L21/02164 ,  H01L21/022 ,  H01L21/02271 ,  H01L21/02274 ,  H01L21/0234 ,  H01L21/31053 ,  H01L21/31608

摘要： A method for forming an insulator layer with enhanced uniformity when planarized through a Chemical-Mechanical Polish (CMP) planarizing process. There is first provided a semiconductor substrate having formed thereupon a patterned layer. The patterned layer has a volume density greater than the volume density of an insulator layer to be formed upon the patterned layer. The patterned layer also has a first region having a high areal density of the patterned layer and a second region having a low areal density of the patterned layer. The second region of the patterned layer is then masked. The first region of the patterned layer is then exposed to a first plasma which is capable of modifying the first region of the patterned layer such that the insulator layer will form less rapidly upon the first region of the patterned layer than upon the second region of the patterned layer. The second region of the semiconductor substrate is then unmasked and the insulator layer is formed upon the patterned layer. The insulator layer so formed being thicker over the second region than over the first region. As a first alternative the first region of the patterned layer may be masked and the second region of the patterned layer exposed to a second plasma which enhances the growth of the insulator layer. As a second alternative, both the first plasma and the second plasma may be employed through sequential masking steps.

摘要翻译： 一种通过化学机械抛光（CMP）平坦化工艺平坦化时形成具有增强的均匀性的绝缘体层的方法。 首先提供了在其上形成图案化层的半导体衬底。 图案化层的体积密度大于在图案化层上形成的绝缘体层的体积密度。 图案化层还具有图案化层的具有高面密度的第一区域和具有低图案层的低密度的第二区域。 然后掩蔽图案化层的第二区域。 然后，图案化层的第一区域暴露于第一等离子体，其能够修饰图案化层的第一区域，使得绝缘体层在图案化层的第一区域上比在第二区域 图案层。 然后，半导体衬底的第二区域未屏蔽，并且在图案化层上形成绝缘体层。 如此形成的绝缘体层在第二区域上比在第一区域之上更厚。 作为第一替代方案，可以对图案化层的第一区域进行掩模，并且图案化层的第二区域暴露于增强绝缘体层生长的第二等离子体。 作为第二替代方案，第一等离子体和第二等离子体都可以通过顺序掩蔽步骤来使用。

公开(公告)号：US5817571A

公开(公告)日：1998-10-06

申请号：US661286

申请日：1996-06-10

申请人： Chen-Hua Douglas Yu ,  Syun-Ming Jang ,  Huang Yuan-Chang

发明人： Chen-Hua Douglas Yu ,  Syun-Ming Jang ,  Huang Yuan-Chang

IPC分类号： H01L21/3105 ,  H01L21/316 ,  H01L21/768 ,  H01L21/44

CPC分类号： H01L21/02129 ,  H01L21/02164 ,  H01L21/022 ,  H01L21/02271 ,  H01L21/02282 ,  H01L21/02304 ,  H01L21/31055 ,  H01L21/31612 ,  H01L21/31625 ,  H01L21/76819

摘要： A method for forming a planarized interlevel dielectric layer without degradation due to microloading effect is described. A first conformal layer of silicon dioxide is deposited overlying a conducting layer over an insulating layer on a semiconductor substrate. A second silicon dioxide layer is deposited overlying the first conformal silicon dioxide layer. A doped glass layer is deposited overlying the second silicon dioxide layer. The doped glass layer is coated with a spin-on-glass layer. The spin-on-glass layer is etched back until the interlevel dielectric layer is planarized. The microloading effects from the etching back of the spin-on-glass layer of the interlevel dielectric layer are lower than microloading effects in a conventional interlevel dielectric layer.

摘要翻译： 描述了由于微加载效应而形成平坦化层间电介质层而不降解的方法。 沉积在半导体衬底上的绝缘层上的导电层的第一保形二氧化硅层。 沉积第二二氧化硅层，覆盖第一共形二氧化硅层。 沉积覆盖第二二氧化硅层的掺杂玻璃层。 掺杂的玻璃层涂覆有旋涂玻璃层。 将旋涂玻璃层回蚀刻直到层间介质层平坦化。 层间电介质层的旋转玻璃层的蚀刻后的微载荷效应低于常规层间电介质层中的微载荷效应。

公开(公告)号：US06479385B1

公开(公告)日：2002-11-12

申请号：US09583397

申请日：2000-05-31

申请人： Syun-Ming Jang ,  Chu-Yun Fu

发明人： Syun-Ming Jang ,  Chu-Yun Fu

IPC分类号： H01L21302

CPC分类号： H01L21/02238 ,  H01L21/02129 ,  H01L21/02164 ,  H01L21/022 ,  H01L21/02255 ,  H01L21/02271 ,  H01L21/02274 ,  H01L21/31612 ,  H01L21/31625 ,  H01L21/76801 ,  H01L21/76837

摘要： A process for forming a composite, interlevel dielectric, (ILD), layer, for MOSFET devices, has been developed. The composite ILD layer is comprised with an underlying, undoped silicon glass layer, providing the material needed to fill the narrow spaces between polysilicon gate structures of the MOSFET devices. A P2O5 doped, insulator layer, is next formed on the underlying, undoped silicon glass layer, to provide a mobile ion gettering property. An overlying, undoped silicon glass layer is then deposited and subjected to a chemical mechanical polishing procedure, resulting in the desired planar top surface topography, for the composite ILD layer.

摘要翻译： 已经开发了用于形成MOSFET器件的复合层间电介质（ILD）层的工艺。 复合ILD层包含底层的未掺杂的硅玻璃层，提供填充MOSFET器件的多晶硅栅极结构之间的狭窄空间所需的材料。 随后在下面未掺杂的硅玻璃层上形成P2O5掺杂的绝缘体层，以提供移动离子吸杂性质。 然后沉积覆盖的未掺杂的硅玻璃层，并进行化学机械抛光程序，得到复合ILD层所需的平面顶表面形貌。

公开(公告)号：US06316348B1

公开(公告)日：2001-11-13

申请号：US09838627

申请日：2001-04-20

申请人： Chu Yun Fu ,  Chia Shiung Tsai ,  Syun-Ming Jang

发明人： Chu Yun Fu ,  Chia Shiung Tsai ,  Syun-Ming Jang

IPC分类号： H01L214763

CPC分类号： H01L21/76829 ,  H01L21/0276 ,  H01L21/0332 ,  H01L21/0337 ,  H01L21/31116 ,  H01L21/3144 ,  H01L21/3145 ,  H01L21/76801 ,  H01L21/7681 ,  H01L21/76813

摘要： The present invention provides an anti-reflective Si-Rich Silicon oxynitride (SiON) etch barrier layer and two compatible oxide etch processes. The Si-Rich Silicon oxynitride (SiON) etch barrier layer can be used as a hard mask in a dual damascene structure and as a hard mask for over a polysilicone gate. The invention has the following key elements: 1) Si rich Silicon oxynitride (SiON) ARC layer, 2) Special Silicon oxide Etch process that has a high selectivity of Si-Rich SiON to silicon oxide or SiN; 3) Special Si Rich SiON spacer process for a self aligned contact (SAC). A dual damascene structure is formed by depositing a first dielectric layer. A novel anti-reflective Si-Rich Silicon oxynitride (SiON) etch barrier layer is deposited on top of the first dielectric layer. A first opening is etched in the first insulating layer. A second dielectric layer is deposited on the anti-reflective Si-Rich Silicon oxynitride (SiON) etch barrier layer. A second dual damascene opening is etched into the dielectric layers. The anti-reflective Si-Rich Silicon oxynnitride (SiON) etch barrier layer can also serve as an ARC layer during these operations to reduce the amount of reflectance from conductive region to reduce distortion of the photoresist pattern.

摘要翻译： 本发明提供了抗反射富Si硅氮化硅（SiON）蚀刻阻挡层和两种相容的氧化物蚀刻工艺。 Si富氧硅氮化物（SiON）蚀刻阻挡层可用作双镶嵌结构中的硬掩模，并且可用作多晶硅栅极上的硬掩模。 本发明具有以下关键要素：1）富硅氧氮化硅（SiON）ARC层，2）具有Si富Si硅对硅氧化物或SiN的高选择性的特殊氧化硅蚀刻工艺; 3）用于自对准接触（SAC）的特殊Si Rich SiON隔离工艺。通过沉积第一介电层形成双镶嵌结构。 在第一介电层的顶部沉积有新的抗反射硅富氮硅氮化硅（SiON）蚀刻阻挡层。 在第一绝缘层中蚀刻第一开口。 第二电介质层沉积在抗反射富Si硅氮化硅（SiON）蚀刻阻挡层上。 第二个双镶嵌开口被蚀刻到电介质层中。 在这些操作期间，抗反射Si富硅氧氮化物（SiON）蚀刻阻挡层也可以用作ARC层，以减少来自导电区域的反射率，以减少光致抗蚀剂图案的变形。

公开(公告)号：US06245682B1

公开(公告)日：2001-06-12

申请号：US09266374

申请日：1999-03-11

申请人： Chu-Yun Fu ,  Syun-Ming Jang

发明人： Chu-Yun Fu ,  Syun-Ming Jang

IPC分类号： H01L21311

CPC分类号： H01L21/32139 ,  H01L21/28123 ,  H01L21/31111 ,  H01L21/3145 ,  Y10S438/952

摘要： This invention relates to the fabrication of integrated circuit devices and more particularly to a method for forming and then later removing a silicon oxynitride, SiON, anti-reflection coating (ARC) over a semiconductor substrate, for the purpose of enhancing the resolution of photolithographically defined sub-micron polysilicon gates. The problem addressed by this invention is that the SiON ARC must first be used to reduce optical reflection from a blanket polysilicon surface, during the photolithography exposure step that defines the sub-micron polysilicon gate features, and then the ARC must be removed by a wet etch process that will not chemically attack the gate oxide under the polysilicon gate features or any exposed polysilicon surfaces. This is accomplished with a fabrication method that uses hot phosphoric acid (H3PO4) to preferentially etch the SiON ARC, relative to the thermal gate oxide, while also using thin thermal oxide layers to protect the polysilicon gate surfaces from being severely attacked by the hot H3PO4. This new method also features the ability to tailor the combination of the composition and thickness of the SiON layer and the thickness of the underlying protective thin thermal oxide layer, in order to minimize the undesired high optical reflectivity of the underlying polysilicon surface.

摘要翻译： 本发明涉及集成电路器件的制造，更具体地说，涉及一种用于在半导体衬底上形成并随后去除氧氮化硅SiON，抗反射涂层（ARC）的方法，用于增强光刻定义的分辨率 亚微米多晶硅门。 本发明解决的问题是，在限定亚微米多晶硅栅极特征的光刻曝光步骤期间，必须首先使用SiON ARC来减少来自覆盖多晶硅表面的光学反射，然后必须通过湿法去除ARC 不会在多晶硅栅极特征或任何暴露的多晶硅表面下化学侵蚀栅极氧化物的蚀刻工艺。 这是通过使用热磷酸（H 3 PO 4）相对于热栅氧化物优先蚀刻SiON ARC的制造方法实现的，同时还使用薄的热氧化物层来保护多晶硅栅极表面免受热H3PO4的严重攻击 。 这种新方法还具有能够定制SiON层的组成和厚度以及下面的保护性薄热氧化物层的厚度的组合，以便使底层多晶硅表面的不期望的高光学反射率最小化。

公开(公告)号：US06245669B1

公开(公告)日：2001-06-12

申请号：US09245564

申请日：1999-02-05

申请人： Chu Yun Fu ,  Chia Shiung Tsai ,  Syun-Ming Jang

发明人： Chu Yun Fu ,  Chia Shiung Tsai ,  Syun-Ming Jang

IPC分类号： H01L214763

CPC分类号： H01L21/76829 ,  H01L21/0276 ,  H01L21/0332 ,  H01L21/0337 ,  H01L21/31116 ,  H01L21/3144 ,  H01L21/3145 ,  H01L21/76801 ,  H01L21/7681 ,  H01L21/76813

摘要： The present invention provides an anti-reflective Si-Rich Silicon oxynitride (SiON) etch barrier layer and two compatible oxide etch processes. The Si-Rich Silicon oxynitride (SiON) etch barrier layer can be used as a hard mask in a dual damascene structure and as a hard mask for over a polysilicon gate. The invention has the following key elements: 1) Si rich Silicon oxynitride (SiON) ARC layer, 2) Special Silicon oxide Etch process that has a high selectivity of Si-Rich SiON to silicon oxide or SiN; 3) Special Si Rich SiON spacer process for a self aligned contact (SAC). A dual damascene structure is formed by depositing a first dielectric layer. A novel anti-reflective Si-Rich Silicon oxynitride (SiON) etch barrier layer is deposited on top of the first dielectric layer. A first opening is etched in the first insulating layer. A second dielectric layer is deposited on the anti-reflective Si-Rich Silicon oxynitride (SiON) etch barrier layer. A second dual damascene opening is etched into the dielectric layers. The anti-reflective Si-Rich Silicon oxynitride (SiON) etch barrier layer can also serve as an ARC layer during these operations to reduce the amount of reflectance from conductive region to reduce distortion of the photoresist pattern.

摘要翻译： 本发明提供了抗反射富Si硅氮化硅（SiON）蚀刻阻挡层和两种相容的氧化物蚀刻工艺。 Si富氧硅氮化物（SiON）蚀刻阻挡层可用作双镶嵌结构中的硬掩模，并可用作多晶硅栅极上的硬掩模。 本发明具有以下关键要素：1）富硅氧氮化硅（SiON）ARC层，2）具有Si富Si硅对硅氧化物或SiN的高选择性的特殊氧化硅蚀刻工艺; 3）用于自对准接触（SAC）的特殊Si Rich SiON隔离工艺。通过沉积第一介电层形成双镶嵌结构。 在第一介电层的顶部沉积有新的抗反射硅富氮硅氮化硅（SiON）蚀刻阻挡层。 在第一绝缘层中蚀刻第一开口。 第二电介质层沉积在抗反射富Si硅氮化硅（SiON）蚀刻阻挡层上。 第二个双镶嵌开口被蚀刻到电介质层中。 在这些操作期间，抗反射硅富氮硅氮化物（SiON）蚀刻阻挡层也可以用作ARC层，以减少来自导电区域的反射率，以减少光致抗蚀剂图案的失真。

公开(公告)号：US06207483B1

公开(公告)日：2001-03-27

申请号：US09527183

申请日：2000-03-17

申请人： Chu-Yun Fu ,  Chung-Long Chang ,  Syun-Ming Jang ,  Shwangming Jeng

发明人： Chu-Yun Fu ,  Chung-Long Chang ,  Syun-Ming Jang ,  Shwangming Jeng

IPC分类号： H01L218238

CPC分类号： H01L21/823828 ,  H01L21/28035 ,  H01L21/32115

摘要： There is provided a method for smoothing the surface of undoped polysilicon regions of a CMOS structure, primarily gate regions. A direct HPD-CVD argon sputter is used improve the surface roughness by a factor of more than 50%. The argon plasma sputter may be used either alone or in conjunction with a thin capping layer of oxide, nitride or oxynitride. The devices manufactured using the process exhibit excellent electrical characteristics and improved reliability compared to devices made using conventional manufacturing processes.

摘要翻译： 提供了一种用于平滑CMOS结构的未掺杂多晶硅区域的表面的方法，主要是栅极区域。 使用直接HPD-CVD氩溅射将表面粗糙度提高了50％以上。 氩等离子体溅射可以单独使用或与氧化物，氮化物或氮氧化物的薄覆盖层结合使用。 与使用常规制造工艺制造的器件相比，使用该工艺制造的器件表现出优异的电气特性和改进的可靠性。