公开(公告)号：US10825741B2

公开(公告)日：2020-11-03

申请号：US16196413

申请日：2018-11-20

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Hui Zang ,  Ruilong Xie

IPC: H01L21/8238 ,  H01L29/66 ,  H01L29/78 ,  H01L21/762 ,  H01L27/092

Abstract: One illustrative IC product disclosed herein includes an isolation structure that separates a fin into a first fin portion and a second fin portion, an epi semiconductor material positioned on the first fin portion in a source/drain region of a transistor device, wherein a lateral gap is present between a first sidewall of the epi semiconductor material and a second sidewall of the SDB isolation structure, and a conductive source/drain structure that is conductively coupled to the epi semiconductor material, wherein a gap portion of the conductive source/drain structure is positioned in the gap and physically contacts the first sidewall and the second sidewall.

公开(公告)号：US20200342918A1

公开(公告)日：2020-10-29

申请号：US16393050

申请日：2019-04-24

Applicant: GLOBALFOUNDRIES INC. ,  MARVELL INTERNATIONAL LTD

Inventor： Venkatraghavan Bringivijayaraghavan ,  Anoop Delampady ,  Puneet Suri

IPC: G11C7/06 ,  G11C11/419 ,  G11C11/412 ,  G11C7/12 ,  G11C7/08

Abstract: Disclosed is a skewed sense amplifier with data and reference sides. The data side has two or more series connected n-type field effect transistors (NFETs) between a data input/output node and a switch to a ground. The reference side has one or more series connected NFETs (but fewer than on the data side) between a reference input/output node and the switch. The data input/output node controls the NFET(s) on the reference side and vice versa. Due to a faster current flow rate through the reference side NFET(s) as compared to the data side NFETs, this amplifier is particularly suited for detecting when, at the initiation of a sensing process, the reference input/output node has a high voltage state and the data input/output node has either a high voltage state or a discharging voltage state. Also disclosed is a memory circuit that incorporates such amplifiers for single-ended read operations.

公开(公告)号：US10818807B2

公开(公告)日：2020-10-27

申请号：US16253191

申请日：2019-01-21

Applicant: GLOBALFOUNDRIES INC.

Inventor： Ajey Poovannummoottil Jacob ,  Theodore J. Letavic ,  Abu Thomas ,  Yusheng Bian

IPC: H01L31/02 ,  H01L31/18 ,  G02B1/11 ,  G02B5/08 ,  H01L31/0232 ,  H01L31/0216 ,  G02B1/113

Abstract: The present disclosure generally relates to semiconductor detectors for use in optoelectronic devices and integrated circuit (IC) chips, and methods for forming same. More particularly, the present disclosure relates to integration of semiconductor detectors with Bragg reflectors. The photodetector of the present disclosure includes a substrate, a Bragg reflector disposed on the substrate, and a semiconductor detector disposed on the Bragg reflector. The Bragg reflector includes alternating layers of a semiconductor material and a dielectric material.

公开(公告)号：US10818803B1

公开(公告)日：2020-10-27

申请号：US16516623

申请日：2019-07-19

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Julien Frougier ,  Ali Razavieh

IPC: H01L21/00 ,  H01L27/00 ,  H01L29/00 ,  H01L29/786 ,  H01L29/10 ,  H01L21/8238 ,  H01L27/088 ,  H01L29/16

Abstract: Structures for a field-effect transistor and methods of forming structures for a field-effect transistor. A source/drain region is connected with a channel layer, and a gate structure extends across the channel layer. The channel layer is composed of a two-dimensional material.

公开(公告)号：US10818764B2

公开(公告)日：2020-10-27

申请号：US16520670

申请日：2019-07-24

Applicant: GLOBALFOUNDRIES INC.

Inventor： John J. Ellis-Monaghan

IPC: H01L29/423 ,  H01L29/06 ,  H01L29/40 ,  H01L29/66 ,  H01L29/78 ,  H01L29/51

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to poly gate extension source to body contact structures and methods of manufacture. The structure includes: a substrate having a doped region; a gate structure over the doped region, the gate structure having a main body and a gate extension region; and a body contact region straddling over the gate extension region and remote from the main body of the gate structure.

公开(公告)号：US10818498B1

公开(公告)日：2020-10-27

申请号：US16407744

申请日：2019-05-09

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Yanping Shen ,  Haiting Wang ,  Hui Zang

IPC: H01L29/66 ,  H01L21/28 ,  H01L29/78 ,  H01L29/40 ,  H01L21/02 ,  H01L29/417 ,  H01L21/768

Abstract: Structures for a field effect-transistor and methods of forming a structure for a field-effect transistor. A gate electrode arranged adjacent to an outer sidewall spacer and an inner sidewall spacer. The gate electrode has a top surface that is recessed relative to the outer sidewall spacer and the inner sidewall spacer. A gate cap includes a first section of a first width arranged over the first section of the gate electrode and a second section of a second width arranged over the first section of the gate cap and the inner sidewall spacer. The second width is greater than the first width, and the inner sidewall spacer is composed of a low-k dielectric material.

公开(公告)号：US10816727B1

公开(公告)日：2020-10-27

申请号：US16441678

申请日：2019-06-14

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Yusheng Bian ,  Ajey Poovannummoottil Jacob

IPC: G02B6/125 ,  G02B6/136 ,  G02B6/12

Abstract: Structures for a waveguide bend and methods of fabricating a structure for a waveguide bend. A waveguide core has a first section, a second section, and a waveguide bend connecting the first section with the second section. The waveguide core includes a first side surface and a second side surface, the first side surface extends about an inner radius of the waveguide bend, and the second side surface extends about an outer radius of the waveguide bend. The waveguide bend includes a central region and a side region that is arranged adjacent to the central region at the first side surface or the second side surface. The central region has a first thickness, and the side region has a second thickness that is less than the first thickness.

公开(公告)号：US20200335619A1

公开(公告)日：2020-10-22

申请号：US16386902

申请日：2019-04-17

Applicant: GLOBALFOUNDRIES INC.

Inventor： Yanping SHEN ,  Haiting WANG ,  Hui ZANG ,  Jiehui SHU

IPC: H01L29/78 ,  H01L21/8238 ,  H01L21/8234 ,  H01L29/66

Abstract: The present disclosure generally relates to semiconductor structures and, more particularly, to middle of line gate structures and methods of manufacture. The structure includes: a plurality of adjacent gate structures; a bridged gate structure composed of a plurality of the adjacent gate structures; source and drain regions adjacent to the bridged gate structure and comprising source and drain metallization features; and contacts to the bridged gate structure and the source and drain metallization features.

公开(公告)号：US20200335591A1

公开(公告)日：2020-10-22

申请号：US16386363

申请日：2019-04-17

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Michael Aquilino ,  Daniel Jaeger ,  Naved Siddiqui ,  Jessica Dechene ,  Daniel J. Dechene ,  Shreesh Narasimha ,  Natalia Borjemscaia

IPC: H01L29/417 ,  H01L27/088 ,  H01L21/311 ,  H01L21/033 ,  H01L29/40

Abstract: Structures for a field-effect transistor and methods of forming a field-effect transistor. A sidewall spacer is arranged adjacent to a sidewall of a gate electrode, a source/drain region is arranged laterally adjacent to the sidewall spacer, and a contact is arranged over the source/drain region and laterally adjacent to the sidewall spacer. The contact is coupled with the source/drain region. A section of an interlayer dielectric layer is laterally arranged between the contact and the sidewall spacer.

公开(公告)号：US20200328306A1

公开(公告)日：2020-10-15

申请号：US16382184

申请日：2019-04-11

Applicant: GlobalFoundries Inc.

Inventor： Jin Wallner ,  Heng Yang ,  Judson Robert Holt

IPC: H01L29/78 ,  H01L29/10 ,  H01L21/8234 ,  H01L21/84 ,  H01L27/088

Abstract: A method of forming a semiconductor device is provided, which includes providing gate structures over an active region and forming a hard mask segment on the active region positioned between a first gate structure and a second gate structure. Cavities are formed in the active region using the gate structures and the hard mask segment as masking features, wherein each cavity has a width substantially equal to a minimum gate-to-gate spacing of the semiconductor device. Epitaxial material is grown in the cavities to form substantially uniform epitaxial structures in the active region.