公开(公告)号：US07796462B2

公开(公告)日：2010-09-14

申请号：US12034686

申请日：2008-02-21

Applicant: Hong Beom Pyeon

Inventor： Hong Beom Pyeon

IPC: G11C8/00

CPC classification number: G06F13/4291 ,  B60R1/0617

Abstract: A system includes a memory controller and a plurality of memory devices connected in-series that communicate with the memory controller. Each of the memory devices has multiple independent serial ports for receiving and transmitting data. The memory controller a device address (DA) or ID number for designating a device that executes a command. Data contained in the command sent by the memory controller is captured by an individual link control circuit, in response to internally generated clock with appropriate latencies. The captured data is written into a corresponding memory bank. The data stored in one of a plurality of memory banks of one memory device is read in accordance with the addresses issued by the memory controller. The read data is propagated from the memory device through the series-connected memory devices to the memory controller.

Abstract translation: 系统包括与存储器控制器通信的存储器控​​制器和串联连接的多个存储器件。 每个存储器件具有用于接收和发送数据的多个独立串行端口。 存储器控制器用于指定执行命令的设备的设备地址（DA）或ID号。 由存储器控制器发送的命令中包含的数据由单独的链路控制电路捕获，以响应具有适当延迟的内部生成的时钟。 捕获的数据被写入对应的存储体。 根据由存储器控制器发出的地址来读取存储在一个存储器件的多个存储器组之一中的数据。 读取的数据从存储器件通过串联连接的存储器件传播到存储器控制器。

公开(公告)号：US20100182838A1

公开(公告)日：2010-07-22

申请号：US12732745

申请日：2010-03-26

Applicant: Jin-Ki KIM ,  Hong Beom PYEON

Inventor： Jin-Ki KIM ,  Hong Beom PYEON

IPC: G11C16/04 ,  G11C8/18

CPC classification number: G06F3/0611 ,  G06F3/0655 ,  G06F3/0688 ,  G06F13/4243 ,  G11C5/066 ,  G11C7/1021 ,  G11C7/1051 ,  G11C7/1078 ,  G11C8/10 ,  G11C16/06 ,  G11C16/08 ,  G11C16/10 ,  G11C16/16 ,  G11C16/26 ,  G11C16/3459 ,  G11C2207/107 ,  G11C2216/30

Abstract: An apparatus, system, and computer-implemented method for controlling data transfer between a plurality of serial data link interfaces and a plurality of memory banks in a semiconductor memory is disclosed. In one example, a flash memory device with multiple links and memory banks, where the links are independent of the banks, is disclosed. The flash memory devices may be cascaded in a daisy-chain configuration using echo signal lines to serially communicate between memory devices. In addition, a virtual multiple link configuration is described wherein a single link is used to emulate multiple links.

Abstract translation: 公开了一种用于控制半导体存储器中的多个串行数据链路接口和多个存储体之间的数据传输的装置，系统和计算机实现的方法。 在一个示例中，公开了具有多个链路和存储体的闪存器件，其中链路独立于存储体。 闪存器件可以使用回波信号线以菊花链配置级联以在存储器件之间串行通信。 此外，描述了虚拟多链路配置，其中使用单个链路来模拟多个链路。

公开(公告)号：US07752364B2

公开(公告)日：2010-07-06

申请号：US11942173

申请日：2007-11-19

Applicant: HakJune Oh ,  Hong Beom Pyeon ,  Jin-Ki Kim

Inventor： HakJune Oh ,  Hong Beom Pyeon ,  Jin-Ki Kim

IPC: G06F13/00 ,  G06F12/00 ,  G11C7/00 ,  H03K19/003

CPC classification number: G11C7/10 ,  G06F13/1689

Abstract: A system controller communicates with devices in a serial interconnection. The system controller sends a read command, a device address identifying a target device in the serial interconnection and a memory location. The target device responds to the read command to read data in the location identified by the memory location. Read data is provided as an output signal that is transmitted from a last device in the serial interconnection to a data receiver of the controller. The data receiver establishes acquisition instants relating to clocks in consideration of a total flow-through latency in the serial interconnection. Where each device has a clock synchronizer, a propagated clock signal through the serial interconnection is used for establishing the acquisition instants. The read data is latched in response to the established acquisition instants in consideration of the flow-through latency, valid data is latched in the data receiver.

Abstract translation: 系统控制器与串行互连中的设备通信。 系统控制器发送读取命令，标识串行互连中的目标设备的设备地址和存储器位置。 目标设备响应读取命令以读取由存储器位置识别的位置中的数据。 读取数据被提供为从串行互连中的最后一个设备发送到控制器的数据接收器的输出信号。 考虑到串行互连中的总流通延迟，数据接收器建立与时钟有关的采集时刻。 在每个设备具有时钟同步器的情况下，通过串行互连的传播时钟信号用于建立采集时刻。 考虑到流通延迟，响应于建立的采集时刻来读取数据被锁存，有效数据被锁存在数据接收器中。

公开(公告)号：US07751272B2

公开(公告)日：2010-07-06

申请号：US12025866

申请日：2008-02-05

Applicant: Hong Beom Pyeon

Inventor： Hong Beom Pyeon

IPC: G11C8/00

CPC classification number: G11C19/00

Abstract: A system includes a plurality of memory devices connected in-series that communicate with a memory controller. When a memory device receives a command strobe signal indicating the start of a command having an ID number, the memory device is placed in a de-selected state and the ID number is compared to the memory device's device address. Delayed versions of the command strobe signal and the command are forwarded while the memory device is in the de-selected state. If the ID number matches the device address with reference to the ID number, the memory device is placed in a selected state. In the selected state, the memory device may refrain from forwarding the delayed versions of the command strobe signal and the command, such that if there is a match, a truncated part of the command is forwarded before the memory device is placed in the selected state.

Abstract translation: 系统包括与存储器控制器通信的串联连接的多个存储器件。 当存储器装置接收到指示具有ID号的命令的开始的命令选通信号时，将存储器件置于取消选择状态，并将ID号与存储器件的器件地址进行比较。 当存储器件处于取消选择状态时，命令选通信号和命令的延迟版本被转发。 如果ID编号与设备地址相匹配，则将存储设备置于选择状态。 在选择状态下，存储装置可以避免转发命令选通信号和命令的延迟版本，使得如果存在匹配，则在将存储装置置于选择状态之前转发命令的截断部分 。

公开(公告)号：US07747833B2

公开(公告)日：2010-06-29

申请号：US11643850

申请日：2006-12-22

Applicant: Hong Beom Pyeon ,  HakJune Oh ,  Jin-Ki Kim

Inventor： Hong Beom Pyeon ,  HakJune Oh ,  Jin-Ki Kim

IPC: G06F12/00

CPC classification number: G06F13/4022 ,  G11C7/1048 ,  G11C7/18 ,  G11C11/408

Abstract: Provided is a memory system that has a plurality of memory banks and a plurality of link controllers. For each memory bank, there is first switching logic for receiving output for each link controller, and for passing on the output of only one of the link controllers to the memory bank. For each link controller, there is second switching logic for receiving an output of each memory bank, and for passing on the output of only one of the memory banks to the link controller. According to an embodiment of the invention, there is switch controller logic for controlling operation of both the first switching logic and the second switching logic to prevent simultaneous or overlapping access by multiple link controllers to the same memory bank, and for preventing simultaneous or overlapping access to multiple banks by the same link controller.

Abstract translation: 提供了具有多个存储体和多个链接控制器的存储器系统。 对于每个存储体，存在用于接收每个链路控制器的输出并且仅将一个链路控制器的输出传递到存储体的第一切换逻辑。 对于每个链路控制器，存在用于接收每个存储体的输出并且仅将一个存储体的输出传递到链路控制器的第二切换逻辑。 根据本发明的实施例，存在用于控制第一开关逻辑和第二开关逻辑的操作的开关控制器逻辑，以防止多个链路控制器同时或重叠地访问同一存储体，并且用于防止同时或重叠访问 通过相同的链路控制器到多个银行。

公开(公告)号：US20100161877A1

公开(公告)日：2010-06-24

申请号：US12337841

申请日：2008-12-18

Applicant: Hong Beom PYEON

Inventor： Hong Beom PYEON

IPC: G06F12/02

CPC classification number: G06F12/0246 ,  G06F2212/7203

Abstract: A semiconductor device for transferring input data to a non-volatile memory device. The semiconductor device comprises a virtual page buffer including a plurality of data elements; a mask buffer including a corresponding plurality of data elements; control logic circuitry for (i) setting each of the mask buffer data elements to a first logic state upon receipt of a trigger; (ii) causing input data to be written to selected virtual page buffer data elements; and (iii) causing those mask buffer data elements corresponding to the selected virtual page buffer data elements to be set to a different logic state; mask logic circuitry configured to generate masked output data by combining, for each of the virtual page buffer data elements, data read therefrom together with the logic state of the corresponding mask buffer data element; and an output interface configured to release the masked output data towards the non-volatile memory device.

Abstract translation: 一种用于将输入数据传送到非易失性存储器件的半导体器件。 该半导体器件包括一个包含多个数据元素的虚拟页缓冲器; 包括对应的多个数据元素的掩码缓冲器; 控制逻辑电路，用于（i）在接收到触发时将每个掩码缓冲器数据元素设置为第一逻辑状态; （ii）使输入数据被写入所选择的虚拟页面缓冲数据元素; 和（iii）使与所选择的虚拟页面缓冲数据元素相对应的掩码缓冲器数据元素被设置为不同的逻辑状态; 掩模逻辑电路，被配置为通过将每个所述虚拟页缓冲器数据元素与对应的掩码缓冲器数据元素的逻辑状态一起组合来生成被屏蔽的输出数据; 以及输出接口，被配置为向所述非易失性存储器件释放所述被屏蔽的输出数据。

公开(公告)号：US20100091538A1

公开(公告)日：2010-04-15

申请号：US12533732

申请日：2009-07-31

Applicant: Jin-Ki Kim ,  HakJune Oh ,  Hong Beom Pyeon

Inventor： Jin-Ki Kim ,  HakJune Oh ,  Hong Beom Pyeon

IPC: G11C5/02 ,  G11C7/00 ,  G11C5/06

CPC classification number: G11C5/02 ,  G06F13/4234 ,  G06F13/4247 ,  G11C5/04 ,  G11C7/10 ,  G11C7/1003 ,  H01L2224/48145 ,  H01L2224/48227 ,  H01L2924/15311

Abstract: Bridge device architecture for connecting discrete memory devices is disclosed. A bridge device is used in conjunction with a composite memory device including at least one discrete memory device. The bridge device comprises a local control interface connected to the at least one discrete memory device, a local input/output interface connected to the at least one discrete memory device, and a global input/output interface interposed between the local control interface and the local input/output interface. The global input/output interface receives and provides global memory control signals and also receives and provides write data to and read data from the at least one discrete memory device.

Abstract translation: 公开了用于连接分立存储器件的桥接器件架构。 桥接器件与包括至少一个分立存储器件的复合存储器件结合使用。 桥接器件包括连接到至少一个分立存储器件的本地控制接口，连接到至少一个分立存储器件的本地输入/输出接口以及插入在本地控制接口和本地之间的全局输入/输出接口 输入/输出接口。 全局输入/输出接口接收并提供全局存储器控制信号，并且还接收并向至少一个离散存储器件提供写入数据和从其读取数据。

公开(公告)号：US07679976B2

公开(公告)日：2010-03-16

申请号：US12391810

申请日：2009-02-24

Applicant: Hong Beom Pyeon

Inventor： Hong Beom Pyeon

IPC: G11C7/00

CPC classification number: G11C29/32 ,  G11C29/003 ,  G11C29/40 ,  G11C2029/0409 ,  G11C2029/2602

Abstract: A method and system for high speed testing of memories in a multi-device system, where individual devices of the multi-device system are arranged in a serial interconnected configuration. High speed testing is achieved by first writing test pattern data to the memory banks of each device of the multi-device system, followed by local test read-out and comparison of the data in each device. Each device generates local result data representing the absence or presence of a failed bit position in the device. Serial test circuitry in each device compares the local result data with global result data from a previous device. The test circuitry compresses this result of this comparison and provides it to the next device as an updated global result data. Hence, the updated global result data will represent the local result data of all the previous devices.

Abstract translation: 一种用于在多设备系统中对存储器进行高速测试的方法和系统，其中多设备系统的各个设备被布置成串行互连配置。 通过首先将测试模式数据写入多设备系统的每个设备的存储体，然后进行本地测试读取和每个设备中的数据比较来实现高速测试。 每个设备产生表示设备中不存在或存在故障位位置的本地结果数据。 每个设备中的串行测试电路将本地结果数据与来自先前设备的全局结果数据进行比较。 测试电路压缩此比较的结果，并将其作为更新的全局结果数据提供给下一个设备。 因此，更新的全局结果数据将表示所有先前设备的本地结果数据。

公开(公告)号：US20090154629A1

公开(公告)日：2009-06-18

申请号：US12168091

申请日：2008-07-04

Applicant: Hong Beom PYEON ,  Peter Gillingham

Inventor： Hong Beom PYEON ,  Peter Gillingham

IPC: H03D3/24

CPC classification number: H04L7/0331 ,  G06F13/1689 ,  H01L2224/32145 ,  H01L2224/48091 ,  H01L2224/48145 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2225/06562 ,  Y02D10/14 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2924/00012

Abstract: A system includes a memory controller and a plurality of semiconductor devices that are series-connected. Each of the devices has memory core for storing data. The memory controller provides a clock signal for synchronizing the operations of the devices. Each device includes a phase-locked loop (PLL) that is selectively enabled or disabled by a PLL enable signal. In each group, the PLLs of a selected number of devices are enabled by PLL enable signals and the other devices are disabled. The enabled PLL provides a plurality of reproduced clock signals with a phase shift of a multiple of 90° in response to an input clock signal. The data transfer is synchronized with at least one of the reproduced clock signals. In the devices of disabled PLLs, the data transfer is synchronized with the input clock signal. The enabled PLL and disabled PLL cause the devices to be the source and the common synchronous clocking, respectively. The devices can be grouped. The devices of one group can be structured by multiple chip packages.

Abstract translation: 系统包括存储器控制器和串联连接的多个半导体器件。 每个设备具有用于存储数据的存储器核心。 存储器控制器提供用于同步器件的操作的时钟信号。 每个器件包括被PLL使能信号选择性地使能或禁止的锁相环（PLL）。 在每个组中，选定数量的器件的PLL通过PLL使能信号使能，其他器件被禁止。 所启用的PLL响应于输入时钟信号提供多个具有90°的倍数的相移的再现时钟信号。 数据传输与再现的时钟信号中的至少一个同步。 在禁用PLL的器件中，数据传输与输入时钟信号同步。 使能的PLL和禁用的PLL分别使器件成为源和公共同步时钟。 设备可以分组。 一组的器件可以由多个芯片封装构成。

公开(公告)号：US20090122631A1

公开(公告)日：2009-05-14

申请号：US12349756

申请日：2009-01-07

Applicant: Hong Beom PYEON

Inventor： Hong Beom PYEON

IPC: G11C7/00

CPC classification number: G11C11/406 ,  G11C7/04 ,  G11C11/40611 ,  G11C11/40615 ,  G11C11/40626 ,  G11C2211/4061

Abstract: A dynamic random access memory (DRAM) device has an array of DRAM cells of rows by columns. Each DRAM cell of the array is coupled with a wordline of a corresponding row and a bitline of a corresponding column. An entry into and an exit from the self-refresh mode are detected by a mode detector and a self-refresh mode signal is provided. An oscillation circuit generates in response to the self-refresh mode signal generates a basic time period. A first frequency divider/time period multiplier changes the basic time period in accordance with a process variation factor relating to the DRAM device. A second frequency divider/time period multiplier further changes the changed time period in accordance with a temperature change factor relating to the DRAM device. In the self-refresh mode, data stored in the DRAM cells is refreshed. In accordance with the two factors, the DRAM devices perform and achieve reliable self-refresh for variable DRAM cell retention time.

Abstract translation: 动态随机存取存储器（DRAM）器件具有逐列的DRAM单元阵列。 阵列的每个DRAM单元与相应列的相应行和位线的字线相连。 通过模式检测器检测进入和退出自刷新模式，并提供自刷新模式信号。 响应于自刷新模式信号产生的振荡电路产生基本时间段。 第一分频器/时间周期乘法器根据与DRAM器件有关的过程变化因素来改变基本时间周期。 第二分频器/时间周期乘法器还根据与DRAM器件有关的温度变化因素来改变改变的时间周期。 在自刷新模式下，存储在DRAM单元中的数据被刷新。 根据这两个因素，DRAM器件执行并实现可变DRAM单元保留时间的可靠的自刷新。