公开(公告)号：US20080076241A1

公开(公告)日：2008-03-27

申请号：US11641131

申请日：2006-12-19

Applicant: Tsung-Hsun Yang ,  Hsiao-Che Wu ,  Feng-Chun Chen ,  Chien-Hsun Pan

Inventor： Tsung-Hsun Yang ,  Hsiao-Che Wu ,  Feng-Chun Chen ,  Chien-Hsun Pan

IPC: H01L21/3205

CPC classification number: H01L21/32139 ,  H01L21/3211

Abstract: A method for reducing stress between a conductive layer and a mask layer is provided. The method for reducing stress comprises a step of performing a plasma treatment with a nitrogen-containing gas to modify a surface of the conductive layer prior to the formation of the mask layer upon the surface. The method is useful for the manufacture of a gate, and the method for manufacturing the gate comprises the steps of providing a substrate; and sequentially depositing an oxide layer, a conductive layer, and a mask layer on the substrate to form a gate stack structure. The conductive layer is subjected to a surface plasma treatment with a nitrogen-containing gas prior to depositing the mask layer to modify its surface.

Abstract translation: 提供了一种用于减小导电层和掩模层之间的应力的方法。 减少应力的方法包括在表面形成掩模层之前，用含氮气体进行等离子体处理以改变导电层的表面的步骤。 该方法对于制造栅极是有用的，并且用于制造栅极的方法包括以下步骤：提供基板; 并在衬底上依次沉积氧化物层，导电层和掩模层以形成栅叠层结构。 在沉积掩模层以改变其表面之前，用含氮气体对导电层进行表面等离子体处理。

公开(公告)号：US20070210374A1

公开(公告)日：2007-09-13

申请号：US11308906

申请日：2006-05-25

Applicant: Hsiao-Che Wu

Inventor： Hsiao-Che Wu

IPC: H01L31/00

CPC classification number: H01L29/7827 ,  H01L29/456 ,  H01L29/517 ,  H01L29/518 ,  H01L29/66666

Abstract: A vertical-type surrounding gate semiconductor device is described. The semiconductor device comprises a pillar substrate, a collar oxide layer, a metal layer, a drain region, a ground line, a source region, a bit line, a word line, a gate and a gate dielectric layer. The ground line is formed in an opening of the pillar substrate and electrically connected to the pillar substrate, and covers the collar oxide layer and the metal layer. The drain region is formed on the top of the pillar substrate and in the upper portion of the opening. The gate is formed among the word line, the bit line and the pillar substrate. The gate dielectric layer is formed among the gate, the source region, the drain region, the bit line and the pillar substrate.

Abstract translation: 描述了垂直型周围栅极半导体器件。 该半导体器件包括柱状基底，环状氧化物层，金属层，漏极区域，接地线，源极区域，位线，字线，栅极和栅极电介质层。 接地线形成在支柱基板的开口部，与柱基板电连接，覆盖环状氧化物层和金属层。 漏极区域形成在支柱基板的顶部和开口的上部。 栅极形成在字线，位线和柱基板之间。 在栅极，源极区域，漏极区域，位线和柱状基板之间形成栅极电介质层。

公开(公告)号：US07049205B2

公开(公告)日：2006-05-23

申请号：US10971133

申请日：2004-10-25

Applicant: Hsiao Che Wu

Inventor： Hsiao Che Wu

IPC: H01L21/20

CPC classification number: H01L27/10852 ,  H01L27/10817 ,  H01L28/91

Abstract: The present invention discloses a stacked capacitor having interdigital electrodes and method for preparing the same. The stacked capacitor comprises a first interdigital electrode, a second interdigital electrode and a dielectric material sandwiched between the first interdigital electrode and the second interdigital electrode. The first and the second interdigital electrodes comprise a body and a plurality of fingers electrically connected to the body, and the dielectric material can be silicon nitride or silicon oxide. Preferably, fingers of the first interdigital electrode are made of titanium nitride, while fingers of the second interdigital electrode are made of polysilicon. The body of the first and the second interdigital electrodes are preferably made of titanium nitride.

Abstract translation: 本发明公开了一种具有叉指电极的叠层电容器及其制备方法。 叠层电容器包括夹在第一叉指电极和第二叉指电极之间的第一叉指电极，第二指状电极和介电材料。 第一和第二叉指电极包括主体和电连接到主体的多个指状物，并且电介质材料可以是氮化硅或氧化硅。 优选地，第一叉指电极的指状物由氮化钛制成，而第二指状电极的指状物由多晶硅制成。 第一和第二叉指电极的主体优选地由氮化钛制成。

公开(公告)号：US20060035428A1

公开(公告)日：2006-02-16

申请号：US10711574

申请日：2004-09-25

Applicant: Hsiao-Che Wu

Inventor： Hsiao-Che Wu

IPC: H01L21/8244

CPC classification number: H01L27/10867 ,  H01L27/10838 ,  H01L27/1087 ,  H01L27/10876 ,  H01L29/66181 ,  H01L29/945

Abstract: A method of fabricating a dynamic random access memory cell is provided. A substrate having a patterned mask layer thereon and a deep trench therein is provided. The patterned mask layer exposes the deep trench. A deep trench capacitor is formed inside the deep trench. Thereafter, a trench is formed in the substrate on one side of the deep trench capacitor. The trench exposes a portion of the upper electrode of the deep trench capacitor and a portion of the substrate. After that, a semiconductor strip is formed in the trench. A gate dielectric layer is formed over the substrate to cover the exposed semiconductor strip and the substrate. A gate is formed over the gate dielectric layer such that the gate and the semiconductor strip crosses over each other, and the gate-covered portion of the semiconductor strip serves as a channel region.

公开(公告)号：US07919384B2

公开(公告)日：2011-04-05

申请号：US12050649

申请日：2008-03-18

Applicant: Hsiao-Che Wu ,  Ming-Yen Li ,  Wen-Li Tsai

Inventor： Hsiao-Che Wu ,  Ming-Yen Li ,  Wen-Li Tsai

IPC: H01L21/20

CPC classification number: H01L28/91

Abstract: A method of making planar-type bottom electrode for semiconductor device is disclosed. A sacrificial layer structure is formed on a substrate. Multiple first trenches are defined in the sacrificial layer structure, wherein those first trenches are arranged in a first direction. The first trenches are filled with insulating material to form an insulating layer in each first trench. Multiple second trenches are defined in the sacrificial layer structure between the insulating layers, and are arranged in a second direction such that the second trenches intersect the first trenches. The second trenches are filled with bottom electrode material to form a bottom electrode layer in each second trench. The insulating layers separate respectively the bottom electrode layers apart from each other. Lastly, removing the sacrificial layer structure defines a receiving space by two adjacent insulating layers and two adjacent bottom electrode layers.

Abstract translation: 公开了制造半导体器件的平面型底电极的方法。 在基板上形成牺牲层结构。 在牺牲层结构中限定多个第一沟槽，其中这些第一沟槽被布置在第一方向上。 第一沟槽用绝缘材料填充，以在每个第一沟槽中形成绝缘层。 多个第二沟槽被限定在绝缘层之间的牺牲层结构中，并且被布置在第二方向上，使得第二沟槽与第一沟槽相交。 第二沟槽填充有底部电极材料，以在每个第二沟槽中形成底部电极层。 绝缘层分别分开彼此分离的底部电极层。 最后，去除牺牲层结构通过两个相邻的绝缘层和两个相邻的底部电极层限定了接收空间。

公开(公告)号：US20090317982A1

公开(公告)日：2009-12-24

申请号：US12142414

申请日：2008-06-19

Applicant: Ming Yen Li ,  Hsiao Che Wu ,  De Long Chen ,  Wen Li Tsai

Inventor： Ming Yen Li ,  Hsiao Che Wu ,  De Long Chen ,  Wen Li Tsai

IPC: H01L21/31 ,  C23C16/00

CPC classification number: H01L21/0228 ,  C23C16/403 ,  C23C16/405 ,  C23C16/45544 ,  H01L21/02142 ,  H01L21/02164 ,  H01L21/022 ,  H01L21/02205 ,  H01L21/3141 ,  H01L21/31604

Abstract: An atomic layer deposition apparatus comprises a reaction chamber, a heater configured to heat a semiconductor wafer positioned on the heater, an oxidant supply configured to deliver oxidant-containing precursors having different oxidant concentrations to the reaction chamber, and a metal supply configured to deliver a metal-containing precursor to the reaction chamber. The present application also discloses a method for preparing a dielectric structure comprising the steps of placing a substrate in a reaction chamber, performing a first atomic layer deposition process including feeding an oxidant-containing precursor having a relatively lower oxidant concentration and a metal-containing precursor to form an thinner interfacial layer on the substrate, and performing a second atomic layer deposition process including feeding the oxidant-containing precursor having an oxidant concentration higher than that used to grow the first metal oxide layer and the metal-containing precursor into the reaction chamber.

Abstract translation: 原子层沉积装置包括反应室，被配置为加热位于加热器上的半导体晶片的加热器，被配置为将具有不同氧化剂浓度的含氧化剂的前体输送到反应室的氧化剂供应源，以及被配置为输送 含金属的前体到反应室。 本申请还公开了一种制备电介质结构的方法，包括以下步骤：将基底放置在反应室中，执行第一原子层沉积工艺，包括进料含氧化剂浓度较低的含氧化剂的前体和含金属的前体 在衬底上形成较薄的界面层，并且执行第二原子层沉积工艺，包括将氧化剂浓度高于用于将第一金属氧化物层和含金属的前体生长的氧化剂浓度进料到反应室中 。

公开(公告)号：US20090189246A1

公开(公告)日：2009-07-30

申请号：US12178154

申请日：2008-07-23

Applicant: Hsiao-Che WU ,  Ming-Yen LI ,  Wen-Li TSAI

Inventor： Hsiao-Che WU ,  Ming-Yen LI ,  Wen-Li TSAI

IPC: H01L21/762 ,  H01L23/58

CPC classification number: H01L21/76224

Abstract: A method for forming a trench isolation structure and a semiconductor device are provided. The method comprises the following steps: forming a patterned mask on a semiconductor substrate; defining a trench with a predetermined depth D by using the patterned mask, wherein the trench has a bottom and a side wall; forming a liner layer covering the bottom and the side wall of the trench; substantially filling the trench with a flowable oxide from the bottom to a thickness d1 to form an oxide layer; forming a barrier layer with a thickness d′ to cover and completely seal the surface of the oxide layer, wherein d′

Abstract translation: 提供了一种用于形成沟槽隔离结构和半导体器件的方法。 该方法包括以下步骤：在半导体衬底上形成图案化掩模; 通过使用图案化掩模来限定具有预定深度D的沟槽，其中沟槽具有底部和侧壁; 形成覆盖所述沟槽的底部和侧壁的衬里层; 用从底部到厚度d1的可流动氧化物基本上填充沟槽以形成氧化物层; 形成厚度d'的阻挡层以覆盖并完全密封氧化物层的表面，其中d'

公开(公告)号：US20080128892A1

公开(公告)日：2008-06-05

申请号：US11566160

申请日：2006-12-01

Applicant: Hsiao Che Wu ,  Yu Min Tsai ,  Wen Li Tsai

Inventor： Hsiao Che Wu ,  Yu Min Tsai ,  Wen Li Tsai

IPC: H01L23/48

CPC classification number: H01L24/11 ,  H01L23/522 ,  H01L23/5329 ,  H01L23/53295 ,  H01L23/562 ,  H01L23/585 ,  H01L24/03 ,  H01L24/10 ,  H01L24/13 ,  H01L2224/0401 ,  H01L2224/13 ,  H01L2224/13099 ,  H01L2924/01005 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01015 ,  H01L2924/01019 ,  H01L2924/01022 ,  H01L2924/01023 ,  H01L2924/01027 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/01033 ,  H01L2924/01038 ,  H01L2924/0104 ,  H01L2924/01044 ,  H01L2924/01047 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01077 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/04941 ,  H01L2924/04953 ,  H01L2924/05042 ,  H01L2924/14 ,  H01L2924/00

Abstract: An integrated circuit device comprises a substrate, a stack structure including circuit structure having conductive lines positioned on the substrate, a reinforcement structure including at least one supporting member positioned on the substrate and a roof covering the circuit structure and the supporting member and at least one bonding pad positioned on the roof and electrically connected to the conductive lines. A method for preparing an integrated circuit device comprises forming a stack structure including circuit structure having conductive lines on a substrate, forming a reinforcement structure including at least one supporting member on the substrate and a roof covering the supporting member and the circuit structure and forming at least one bonding pad on the roof and electrically connecting to the conductive lines.

Abstract translation: 集成电路装置包括基板，包括具有位于基板上的导线的电路结构的堆叠结构，包括位于基板上的至少一个支撑构件和覆盖电路结构和支撑构件的顶板的加强结构以及至少一个 接合垫定位在屋顶上并电连接到导电线。 一种集成电路器件的制造方法，其特征在于，在基板上形成具有导线的电路结构的堆叠结构，形成包括所述基板上的至少一个支撑部件的加强结构以及覆盖所述支撑部件和所述电路结构的屋顶， 至少一个焊盘在屋顶上并且电连接到导电线。

公开(公告)号：US06393210B1

公开(公告)日：2002-05-21

申请号：US09469146

申请日：1999-12-21

Applicant: Hsiao-Che Wu

Inventor： Hsiao-Che Wu

IPC: F26B1900

CPC classification number: H01L21/67115

Abstract: An apparatus for the rapid thermal processing of a semiconductor wafer is disclosed. The apparatus includes a preheat unit for preheating a gas composition, and a RTP reactor having a processing chamber and a heat source for heating the wafer. The processing chamber has a wafer holder, and a gas inlet and a gas outlet through which the preheated gas composition flows in and out of the processing chamber.

Abstract translation: 公开了一种用于半导体晶片快速热处理的装置。 该装置包括用于预热气体组合物的预热单元，以及具有用于加热晶片的处理室和热源的RTP反应器。 处理室具有晶片保持器，以及气体入口和气体出口，预热气体组合物通过该出口和气体出口流入和流出处理室。