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    Method and maintenance device for automatic maintenance of an autonomous dialysis system
    31.
    发明授权
    Method and maintenance device for automatic maintenance of an autonomous dialysis system 有权

    公开(公告)号：US11992597B2

    公开(公告)日：2024-05-28

    申请号：US17728637

    申请日：2022-04-25

    Applicant: IMEC VZW ,  Stichting IMEC Nederland

    Inventor： Fokko Wieringa ,  Willem Van Roy ,  Patrick van Deursen ,  Lucas Lindeboom

    IPC: A61M1/36

    CPC classification number: A61M1/3672 ,  A61M2205/70

    Abstract: According to an aspect there is provided a method for automatic maintenance of a dialysis system. The dialysis system includes a plurality of filter sections where each filter section includes a blood flow channel, a dialysate flow channel, and a membrane separating the blood flow channel from the dialysate flow channel and having a plurality of pores through which substances are exchanged between a blood flow in the blood flow channel and a dialysate flow in the dialysate flow channel. The method includes determining, for each filter section of the plurality of filter sections, whether a maintenance criterion is fulfilled. The method also includes triggering a maintenance event for a filter section of the plurality of filter sections for which the maintenance criterion is fulfilled. The method also includes executing the maintenance event and optionally administering a thrombolytic agent to the blood flow channel of the filter section.

    METHOD FOR INTERCONNECTING A BURIED WIRING LINE AND A SOURCE/DRAIN BODY
    32.
    发明公开
    METHOD FOR INTERCONNECTING A BURIED WIRING LINE AND A SOURCE/DRAIN BODY 审中-公开

    公开(公告)号：US20240136225A1

    公开(公告)日：2024-04-25

    申请号：US18486370

    申请日：2023-10-12

    Applicant: IMEC VZW

    Inventor： Boon Teik Chan ,  Hans Mertens ,  Zsolt Tokei ,  Naoto Horiguchi

    IPC: H01L21/768 ,  H01L23/528 ,  H01L29/40

    CPC classification number: H01L21/76879 ,  H01L21/76802 ,  H01L23/5286 ,  H01L29/401

    Abstract: A method provided for interconnecting a buried wiring line and a source/drain body. The method includes: forming a fin structure on a substrate, the fin structure comprising at least one channel layer; forming a buried wiring line in a trench extending alongside the fin structure, wherein the buried wiring line is capped by a first insulating layer structure; forming a source/drain body on the at least one channel layer by epitaxy; forming a via hole in the first insulating layer structure to expose an upper surface of the buried wiring line; forming a metal via in the via hole; forming a second insulating layer structure over the first insulating layer structure, wherein a contact opening is defined in the second insulating layer structure to expose the source/drain body and an upper via portion of the metal via; and forming a source/drain contact in the contact opening, on the upper via portion and the source/drain body, thereby inter-connecting the buried wiring line and the source/drain body.

    Item inspection by radiation imaging using an iterative projection-matching approach
    34.
    发明授权
    Item inspection by radiation imaging using an iterative projection-matching approach 有权

    公开(公告)号：US11927586B2

    公开(公告)日：2024-03-12

    申请号：US17252145

    申请日：2019-07-01

    Applicant: UNIVERSITEIT ANTWERPEN ,  IMEC VZW

    Inventor： Jan De Beenhouwer ,  Jan Sijbers

    IPC: G06K9/00 ,  G01N23/046 ,  G01N33/36 ,  G06T7/00

    CPC classification number: G01N33/367 ,  G01N23/046 ,  G06T7/0004 ,  G01N2223/401 ,  G01N2223/405 ,  G01N2223/419 ,  G06T2207/30124

    Abstract: A method and system for inspection of an item, and a use thereof, are presented. The method comprises acquiring a plurality of projection images of an item at a plurality of projection angles for performing a tomographic reconstruction of the item. A plurality of objects are detected in the tomographic reconstruction and each object has a generic shape described by a parametric three-dimensional numerical model. Said detection comprises determining initial estimates of position and/or orientation of each object and at least one geometrical parameter of the three-dimensional model for each object. The initial estimates are iteratively refining by using a projection-matching approach, in which forward projection images are simulated for the objects according to operating parameters of the radiation imaging device and a difference metric between acquired projection images and simulated forward projection images is reduced at each iteration step.

    Method for Continuous Photovoltaic Cell Stringing and Photovoltaic Cell Assembly
    36.
    发明公开
    Method for Continuous Photovoltaic Cell Stringing and Photovoltaic Cell Assembly 审中-公开

    公开(公告)号：US20240063326A1

    公开(公告)日：2024-02-22

    申请号：US18448542

    申请日：2023-08-11

    Applicant: IMEC VZW ,  UNIVERSITEIT HASSELT

    Inventor： Tom Borgers ,  Marc Meuris

    IPC: H01L31/20 ,  H01L31/18 ,  H01L31/05 ,  H10K30/57 ,  H10K71/60

    CPC classification number: H01L31/206 ,  H01L31/1804 ,  H01L31/202 ,  H01L31/0504 ,  H10K30/57 ,  H10K71/60

    Abstract: Example embodiments relate to methods for continuous photovoltaic cell stringing and photovoltaic cell assemblies. An example method includes providing a foil in a provision direction in a continuous manner. The method also includes cutting at least one slit into the foil along the provision direction. Additionally, the method includes creating at least one slit opening by folding open the foil at a location of the at least one slit. Further, the method includes providing at least one electrically conductive wire near a first surface of the foil along the provision direction aligned with the at least one slit opening in a continuous manner. Yet further, the method includes folding back the foil at the at least one slit opening after the electrically conductive wire provision such that the at least one electrically conductive wire changes its position.

    SFQ-based Pulse-conserving Logic Gates
    37.
    发明公开
    SFQ-based Pulse-conserving Logic Gates 审中-公开

    公开(公告)号：US20240039541A1

    公开(公告)日：2024-02-01

    申请号：US17815368

    申请日：2022-07-27

    Applicant: IMEC VZW

    Inventor： Quentin Paul Herr ,  Anna Yurievna Herr

    IPC: H03K19/23 ,  H03K19/17736 ,  H01L39/24

    CPC classification number: H03K19/23 ,  H03K19/1774 ,  H01L39/2493

    Abstract: Josephson junction based logic devices and methods for their use are described. An example Josephson junction based logic device includes a two-input OR/AND (OA2) gate. The OA2 gate includes a first input node inductively coupled to a first input source and a second input node inductively coupled to a second input source. The first and second input sources are configured to provide single-flux-quantum (SFQ) pulses. The OA2 gate also includes first plurality of inductors coupled between the first input node and one of: a first output node or a second output node. The OA2 gate additionally includes a second plurality of inductors coupled between the second input node and one of: the first or the second output nodes. The OA2 gate also includes Josephson junctions coupled between a common node and one of: the first or the second input node, or the first or the second output node.

    SUPERCONDUCTIVE INTERCONNECT STRUCTURE
    38.
    发明公开
    SUPERCONDUCTIVE INTERCONNECT STRUCTURE 审中-公开

    公开(公告)号：US20240038589A1

    公开(公告)日：2024-02-01

    申请号：US17877500

    申请日：2022-07-29

    Applicant: IMEC VZW

    Inventor： Anna Yurievna HERR ,  Quentin Paul HERR ,  Zsolt TOKEI ,  Anshul GUPTA

    IPC: H01L21/768 ,  H01L23/522

    CPC classification number: H01L21/76897 ,  H01L21/76885 ,  H01L23/5226 ,  H01L23/53285

    Abstract: A method for forming a superconducting interconnect structure, comprising: providing a substrate, forming a superconductive layer, forming a layer of a first dielectric material, removing parts of the layer of the first dielectric material and of the superconductive layer so as to form a pattern comprising a first set of line structures comprising: a first set of superconductive line structures, and a first set of line structures made of the first dielectric material, forming a second dielectric material between the line structures of the first set, forming a layer formed of a third dielectric material, providing a patterned mask, transferring the pattern into the first dielectric material and into the layer formed of the third dielectric material, so as to form the at least one via hole, removing the patterned mask, and forming a superconductive material layer so as to form at least one via.

    Method for Forming an Interconnect Structure
    39.
    发明公开
    Method for Forming an Interconnect Structure 审中-公开

    公开(公告)号：US20240036470A1

    公开(公告)日：2024-02-01

    申请号：US18356700

    申请日：2023-07-21

    Applicant: IMEC VZW

    Inventor： Waikin Li ,  Zheng Tao

    IPC: G03F7/11 ,  G03F7/00 ,  G03F1/38 ,  G03F1/56 ,  G03F7/09

    CPC classification number: G03F7/11 ,  G03F7/0035 ,  G03F1/38 ,  G03F1/56 ,  G03F7/094

    Abstract: A method is provided for forming an interconnect structure for an integrated circuit. The method includes: forming a metal layer over a substrate; forming a hard mask layer over the metal layer; forming a first resist layer of a first resist material over the hard mask layer and patterning the first resist layer in a first lithography process to define a first resist pattern; forming over the first resist pattern a second resist layer of a second resist material different from the first resist material and patterning the second resist layer in a second lithography process to define a second resist pattern of resist lines extending in parallel along a first direction, wherein at least a portion of the first resist pattern is overlapped by the second resist pattern; patterning the hard mask layer using the second resist pattern as an etch mask to define a hard mask line pattern underneath the second resist pattern, and subsequently the metal layer to define a metal line pattern underneath the hard mask line pattern; removing the second resist pattern and subsequently patterning the hard mask line pattern using said at least a portion of the first resist pattern as an etch mask to define a hard mask pillar pattern over the metal line pattern; and forming a metal pillar pattern in accordance with the hard mask pillar pattern.

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