公开(公告)号：US4566172A

公开(公告)日：1986-01-28

申请号：US583512

申请日：1984-02-24

申请人： Izak Bencuya ,  Adrian I. Cogan

发明人： Izak Bencuya ,  Adrian I. Cogan

IPC分类号： H01L21/335 ,  H01L29/10 ,  H01L21/425

CPC分类号： H01L29/66416 ,  H01L29/1066

摘要： Junction field effect transistor, specifically a static induction transistor and method of fabricating. A low resistivity N-type layer is formed at the surface of a high resistivity N-type epitaxial layer which has been grown on a low resistivity N-type substrate of silicon. The surface of the low resistivity N-type layer is coated with silicon nitride, portions of the silicon nitride are removed and the silicon is etched to form parallel grooves with interposed ridges of silicon. Silicon dioxide is grown in the grooves, removed from the end walls of the grooves, and P-type zones are formed at the end walls of the grooves. The depth of the grooves is increased by etching to remove most of the P-type zone underlying each groove while leaving laterally extending P-type portions. Oxygen is implanted to convert the remainder of the P-type zones underlying the end walls of the grooves to silicon dioxide. Metal layers are deposited in the bottoms of the grooves making contact with the P-type portions. The grooves are filled with filler material and materials are etched away to produce a flat, planar surface with low resistivity N-type silicon of the ridges exposed in the surface and with filler material in the grooves also exposed at the surface. A large area metal contact is applied which extends across the surface and makes ohmic contact to the low resistivity N-type silicon of all the ridges.

摘要翻译： 结型场效应晶体管，特别是静态感应晶体管及其制造方法。 在低电阻N型硅衬底上生长的高电阻率N型外延层的表面形成低电阻率N型层。 低电阻率N型层的表面涂覆有氮化硅，部分氮化硅被去除并且蚀刻硅以形成具有插入的硅脊的平行凹槽。 在凹槽中生长二氧化硅，从凹槽的端壁移除，并且在凹槽的端壁处形成P型区域。 通过蚀刻来增加凹槽的深度以去除每个凹槽下面的大部分P型区域，同时留下横向延伸的P型部分。 植入氧气以将槽的端壁下面的P型区域的其余部分转化为二氧化硅。 金属层沉积在与P型部分接触的凹槽的底部。 凹槽填充有填充材料，并且材料被蚀刻掉以产生平坦的平坦表面，其表面露出的脊的电阻率低的N型硅，并且槽中的填充材料也暴露在表面。 施加大面积金属接触，其延伸穿过表面并与所有脊的低电阻率N型硅欧姆接触。

公开(公告)号：US10148106B2

公开(公告)日：2018-12-04

申请号：US15595714

申请日：2017-05-15

申请人： Izak Bencuya

发明人： Izak Bencuya

IPC分类号： H02J7/02 ,  H02J7/00 ,  H01R13/66 ,  H01R13/713 ,  H01R13/703

摘要： A power connector for use in charging a battery of a device is provided. The power connector has an electromagnetic switch having terminals used to supply power from an external power source to a power adapter which is connected to the battery of the device. A power sensing circuit is coupled between the terminals of the electromagnetic switch and the power adapter, wherein the electromagnetic switch is configured to shut off power supplied to the power adapter when the power sensing circuit detects that the battery is fully charged. A reset mechanism is configured to mechanically activate the electromagnetic switch to start supplying power to the power adapter.

公开(公告)号：US07745289B2

公开(公告)日：2010-06-29

申请号：US10997818

申请日：2004-11-24

申请人： Izak Bencuya ,  Brian Sze-Ki Mo ,  Ashok Challa

发明人： Izak Bencuya ,  Brian Sze-Ki Mo ,  Ashok Challa

IPC分类号： H01L21/336

CPC分类号： H01L29/7813 ,  H01L29/0847 ,  H01L29/42368

摘要： In accordance with an exemplary embodiment of the invention, a substrate of a first conductivity type silicon is provided. A substrate cap region of the first conductivity type silicon is formed such that a junction is formed between the substrate cap region and the substrate. A body region of a second conductivity type silicon is formed such that a junction is formed between the body region and the substrate cap region. A trench extending through at least the body region is then formed. A source region of the first conductivity type is then formed in an upper portion of the body region. An out-diffusion region of the first conductivity type is formed in a lower portion of the body region as a result of one or more temperature cycles such that a spacing between the source region and the out-diffusion region defines a channel length of the field effect transistor.

摘要翻译： 根据本发明的示例性实施例，提供了第一导电型硅的衬底。 形成第一导电型硅的衬底帽区域，使得在衬底帽区域和衬底之间形成结。 形成第二导电型硅的体区，使得在体区和衬底帽区之间形成接合部。 然后形成至少延伸穿过身体区域的沟槽。 然后在身体区域的上部形成第一导电类型的源极区域。 作为一个或多个温度循环的结果，第一导电类型的扩散区形成在体区的下部，使得源极区域和外扩散区域之间的间隔限定了场的沟道长度 效应晶体管。

公开(公告)号：US07736978B2

公开(公告)日：2010-06-15

申请号：US11503506

申请日：2006-08-10

申请人： Brian Sze-Ki Mo ,  Duc Chau ,  Steven Sapp ,  Izak Bencuya ,  Dean Edward Probst

发明人： Brian Sze-Ki Mo ,  Duc Chau ,  Steven Sapp ,  Izak Bencuya ,  Dean Edward Probst

IPC分类号： H01L21/336

CPC分类号： H01L29/7813 ,  H01L29/0619 ,  H01L29/0696 ,  H01L29/0869 ,  H01L29/1095 ,  H01L29/407 ,  H01L29/4236 ,  H01L29/66734 ,  H01L29/7811

摘要： A trenched field effect transistor is provided that includes (a) a semiconductor substrate, (b) a trench extending a predetermined depth into the semiconductor substrate, (c) a pair of doped source junctions, positioned on opposite sides of the trench, (d) a doped heavy body positioned adjacent each source junction on the opposite side of the source junction from the trench, the deepest portion of the heavy body extending less deeply into said semiconductor substrate than the predetermined depth of the trench, and (e) a doped well surrounding the heavy body beneath the heavy body.

公开(公告)号：US20070042551A1

公开(公告)日：2007-02-22

申请号：US11503506

申请日：2006-08-10

申请人： Brian Mo ,  Duc Chau ,  Steven Sapp ,  Izak Bencuya ,  Dean Probst

发明人： Brian Mo ,  Duc Chau ,  Steven Sapp ,  Izak Bencuya ,  Dean Probst

IPC分类号： H01L21/336

CPC分类号： H01L29/7813 ,  H01L29/0619 ,  H01L29/0696 ,  H01L29/0869 ,  H01L29/1095 ,  H01L29/407 ,  H01L29/4236 ,  H01L29/66734 ,  H01L29/7811

摘要： A trenched field effect transistor is provided that includes (a) a semiconductor substrate, (b) a trench extending a predetermined depth into the semiconductor substrate, (c) a pair of doped source junctions, positioned on opposite sides of the trench, (d) a doped heavy body positioned adjacent each source junction on the opposite side of the source junction from the trench, the deepest portion of the heavy body extending less deeply into said semiconductor substrate than the predetermined depth of the trench, and (e) a doped well surrounding the heavy body beneath the heavy body.

摘要翻译： 提供了沟槽场效应晶体管，其包括（a）半导体衬底，（b）在半导体衬底中延伸预定深度的沟槽，（c）位于沟槽相对侧上的一对掺杂源极结（d ）掺杂的重体，其位于与沟槽的源极结的相对侧上的每个源极结附近，重体的最深部分比沟槽的预定深度更深地延伸到所述半导体衬底中，以及（e）掺杂 很好地围着沉重的身体下面的沉重的身体。

公开(公告)号：US20050079676A1

公开(公告)日：2005-04-14

申请号：US10927788

申请日：2004-08-27

申请人： Brian Mo ,  Duc Chau ,  Steven Sapp ,  Izak Bencuya ,  Dean Probst

发明人： Brian Mo ,  Duc Chau ,  Steven Sapp ,  Izak Bencuya ,  Dean Probst

IPC分类号： H01L21/336 ,  H01L29/06 ,  H01L29/10 ,  H01L29/78

CPC分类号： H01L29/7813 ,  H01L29/0619 ,  H01L29/0696 ,  H01L29/0869 ,  H01L29/1095 ,  H01L29/407 ,  H01L29/4236 ,  H01L29/66734 ,  H01L29/7811

摘要： A trenched field effect transistor is provided that includes (a) a semiconductor substrate, (b) a trench extending a predetermined depth into the semiconductor substrate, (c) a pair of doped source junctions, positioned on opposite sides of the trench, (d) a doped heavy body positioned adjacent each source junction on the opposite side of the source junction from the trench, the deepest portion of the heavy body extending less deeply into said semiconductor substrate than the predetermined depth of the trench, and (e) a doped well surrounding the heavy body beneath the heavy body.

摘要翻译： 提供了沟槽场效应晶体管，其包括（a）半导体衬底，（b）在半导体衬底中延伸预定深度的沟槽，（c）位于沟槽相对侧上的一对掺杂源极结（d ）掺杂的重体，其位于与沟槽的源极结的相对侧上的每个源极结附近，重体的最深部分比沟槽的预定深度更深地延伸到所述半导体衬底中，以及（e）掺杂 很好地围着沉重的身体下面的沉重的身体。

公开(公告)号：US06423623B1

公开(公告)日：2002-07-23

申请号：US09141184

申请日：1998-08-27

申请人： Izak Bencuya ,  Maria Christina B. Estacio ,  Steven P. Sapp ,  Consuelo N. Tangpuz ,  Gilmore S. Baje ,  Rey D. Maligro

发明人： Izak Bencuya ,  Maria Christina B. Estacio ,  Steven P. Sapp ,  Consuelo N. Tangpuz ,  Gilmore S. Baje ,  Rey D. Maligro

IPC分类号： H01L2144

CPC分类号： H01L24/06 ,  H01L23/49562 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/05553 ,  H01L2224/0603 ,  H01L2224/16245 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/48253 ,  H01L2224/48599 ,  H01L2224/48699 ,  H01L2224/49111 ,  H01L2924/01005 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01015 ,  H01L2924/01029 ,  H01L2924/01079 ,  H01L2924/014 ,  H01L2924/10161 ,  H01L2924/10253 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/181 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2924/00012

摘要： A packaging technique that significantly reduces package resistance. According to the invention, lead frames external to the package are brought in direct contact to solder balls on the surface of the silicon die inside the package molding, eliminating resistive wire interconnections. The packaging technique of the present invention is particularly suitable for power transistors.

摘要翻译： 一种显着降低封装电阻的封装技术。 根据本发明，封装外部的引线框架与封装模制件内的硅芯片表面上的焊球直接接触，消除了电阻线互连。 本发明的封装技术特别适用于功率晶体管。

公开(公告)号：US5767550A

公开(公告)日：1998-06-16

申请号：US731598

申请日：1996-10-16

申请人： Daniel Calafut ,  Izak Bencuya ,  Steven Sapp

发明人： Daniel Calafut ,  Izak Bencuya ,  Steven Sapp

IPC分类号： H01L27/02 ,  H01L29/78 ,  H01L23/62

CPC分类号： H01L29/7808 ,  H01L27/0251 ,  H01L27/0255 ,  H01L29/7811 ,  H01L29/402 ,  H01L2924/0002 ,  Y10S148/126 ,  Y10S148/174 ,  Y10S438/983

摘要： In one embodiment, modifications to the polysilicon gate, body, source, and contact masks of a DMOS process add a source-body monocrystalline gate protection diode under the gate pad by implanting an anode region beneath the gate. The anode is connected to the gate through the gate metal in the pad. In addition to the gate-source diode, there is also a connection from the drain to the gate through the anode formed by the body region beneath the gate. This embodiment includes a junction terminating field plate. The presence of the field plate creates a special protection device similar to a zener diode, but which exhibits a current/voltage characteristic similar to a thyristor. A significant feature of this embodiment is that the zener breakdown voltage is easily adjusted by a simple modification to the fabrication process. The field plate creates two opposing junctions with the spacing determined by the length of the field plate. The concentration gradients under the field plate, and hence the breakdown voltage, is controlled by suitable length of the field plate and other processing conditions. A zener breakdown programmability option is implemented so that the zener breakdown voltage is varied by suitable process selection using only one additional implant, temperature cycle, and photolithographic mask. The zener diode gate protection structure formed using the field plate has a high current per unit power; therefore, a much smaller protection structure can be implemented compared to the prior art, because much more current is conducted for a given size structure.

摘要翻译： 在一个实施例中，对DMOS工艺的多晶硅栅极，主体，源极和接触掩模的修改通过在栅极下方注入阳极区域而在栅极焊盘之下添加源体单晶栅极保护二极管。 阳极通过焊盘中的栅极金属连接到栅极。 除了栅极 - 源极二极管之外，还存在从漏极到栅极通过由栅极下方的主体区域形成的阳极的连接。 该实施例包括结终止场板。 场板的存在创建了类似于齐纳二极管的特殊保护装置，但其具有类似于晶闸管的电流/电压特性。 该实施例的显着特征在于，通过对制造工艺的简单修改容易地调整齐纳击穿电压。 场板产生具有由场板长度确定的间距的两个相对的接合点。 场板下的浓度梯度，因此击穿电压由场板的适当长度和其他处理条件控制。 实施齐纳击穿可编程性选项，使得仅使用一个附加植入物，温度循环和光刻掩模的合适的工艺选择来改变齐纳击穿电压。 使用场板形成的齐纳二极管栅极保护结构具有每单位功率的高电流; 因此，与现有技术相比，可以实现更小的保护结构，因为针对给定的尺寸结构进行更多的电流。

公开(公告)号：US5665619A

公开(公告)日：1997-09-09

申请号：US645446

申请日：1996-05-13

申请人： Sze-Hon Kwan ,  Izak Bencuya

发明人： Sze-Hon Kwan ,  Izak Bencuya

IPC分类号： H01L21/336 ,  H01L29/45 ,  H01L29/78 ,  H01L21/265

CPC分类号： H01L29/7813 ,  H01L29/456

摘要： A trench DMOS transistor structure includes a contact to the transistor's source and body that is self-aligned to the trench. With a self-aligned contact, the distance from the edge of the source and body contact to the edge of the trench can be minimized. Thus, the distance between the trench edges can be reduced. As a result, the packing density of the transistor is increased dramatically. This gives rise to much improved performance in terms of low m-resistance and higher current drive capability. Alternate process modules are provided for fabricating the self-aligned contact structure.

摘要翻译： 沟槽DMOS晶体管结构包括与沟槽自对准的晶体管源极和主体的接触。 通过自对准接触，可以将从源极和主体接触的边缘到沟槽的边缘的距离最小化。 因此，可以减小沟槽边缘之间的距离。 结果，晶体管的封装密度急剧增加。 这在低m电阻和更高的电流驱动能力方面产生了大大改进的性能。 提供了用于制造自对准接触结构的交替工艺模块。

公开(公告)号：US5567634A

公开(公告)日：1996-10-22

申请号：US431765

申请日：1995-05-01

申请人： Francois Hebert ,  Sze-Hon Kwan ,  Izak Bencuya

发明人： Francois Hebert ,  Sze-Hon Kwan ,  Izak Bencuya

IPC分类号： H01L21/336 ,  H01L29/45 ,  H01L29/78 ,  H01L21/265

CPC分类号： H01L29/7813 ,  H01L29/456

摘要： A method of fabricating a trench DMOS transistor structure results in the contact to the transistor's source and body being self-aligned to the trench. With a self-aligned contact, the distance from the edge of the source and body contact to the edge of the trench can be minimized. Thus, the distance between the trench edges can be reduced. As a result, the packing density of the transistor is increased dramatically. This gives rise to much improved performance in terms of low on-resistance and higher current drive capability. The process flow maximizes the height of the trench poly gate prior to formation of oxide spacers for the self-contact contact, thereby ensuring sufficient step height for the spacers.

摘要翻译： 制造沟槽DMOS晶体管结构的方法导致与晶体管的源极和主体与沟槽自对准的接触。 通过自对准接触，可以将从源极和主体接触的边缘到沟槽的边缘的距离最小化。 因此，可以减小沟槽边缘之间的距离。 结果，晶体管的封装密度急剧增加。 这在低导通电阻和更高的电流驱动能力方面产生了大大改进的性能。 在形成用于自接触接触的氧化物间隔物之前，工艺流程使沟槽多晶硅栅极的高度最大化，从而确保间隔物的足够的台阶高度。