公开(公告)号：US07915167B2

公开(公告)日：2011-03-29

申请号：US11240440

申请日：2005-09-29

Applicant: Marko Radosavljevic ,  Amlan Majumdar ,  Suman Datta ,  Jack Kavalieros ,  Brian S. Doyle ,  Justin K. Brask ,  Robert S. Chau

Inventor： Marko Radosavljevic ,  Amlan Majumdar ,  Suman Datta ,  Jack Kavalieros ,  Brian S. Doyle ,  Justin K. Brask ,  Robert S. Chau

IPC: H01L21/302

CPC classification number: H01L29/42392 ,  H01L21/28079 ,  H01L21/28194 ,  H01L29/0673 ,  H01L29/41775 ,  H01L29/495 ,  H01L29/51 ,  H01L29/517 ,  H01L29/518 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/66606 ,  H01L29/66636 ,  H01L29/66742 ,  H01L29/7834 ,  H01L29/78618 ,  H01L29/78696 ,  Y10S438/926 ,  Y10S438/957

Abstract: A method for fabricating a field-effect transistor with a gate completely wrapping around a channel region is described. Ion implantation is used to make the oxide beneath the channel region of the transistor more etchable, thereby allowing the oxide to be removed below the channel region. Atomic layer deposition is used to form a gate dielectric and a metal gate entirely around the channel region once the oxide is removed below the channel region.

Abstract translation: 描述了一种制造具有完全围绕通道区域的栅极的场效应晶体管的方法。 离子注入用于使晶体管的沟道区下方的氧化物更易蚀刻，从而允许氧化物在沟道区下方被去除。 一旦氧化物在通道区域下方被去除，原子层沉积被用于在通道区域的整个周围形成栅极电介质和金属栅极。

公开(公告)号：US07863710B2

公开(公告)日：2011-01-04

申请号：US12032579

申请日：2008-02-15

Applicant: Mantu K. Hudait ,  Peter G. Tolchinsky ,  Jack T. Kavalieros ,  Marko Radosavljevic

Inventor： Mantu K. Hudait ,  Peter G. Tolchinsky ,  Jack T. Kavalieros ,  Marko Radosavljevic

IPC: H01L29/20

CPC classification number: H01L21/02664 ,  H01L21/02381 ,  H01L21/02433 ,  H01L21/02461 ,  H01L21/02463 ,  H01L21/02532 ,  H01L21/02546 ,  H01L21/02549 ,  H01L21/02686 ,  H01L21/268

Abstract: Dislocation removal from a group III-V film grown on a semiconductor substrate is generally described. In one example, an apparatus includes a semiconductor substrate, a buffer film including a group III-V semiconductor material epitaxially coupled to the semiconductor substrate wherein the buffer film includes material melted by laser pulse irradiation and recrystallized to substantially remove dislocations or defects from the buffer film, and a first semiconductor film epitaxially grown on the buffer film wherein a lattice mismatch exists between the semiconductor substrate and the first semiconductor film.

Abstract translation: 通常描述从在半导体衬底上生长的III-V族膜脱离脱落。 在一个示例中，一种装置包括半导体衬底，包括外延耦合到半导体衬底的III-V族半导体材料的缓冲膜，其中缓冲膜包括通过激光脉冲照射熔化的材料并重结晶以基本上从缓冲器中去除位错或缺陷 膜，以及在所述缓冲膜上外延生长的第一半导体膜，其中在所述半导体衬底和所述第一半导体膜之间存在晶格失配。

公开(公告)号：US07759142B1

公开(公告)日：2010-07-20

申请号：US12347268

申请日：2008-12-31

Applicant: Prashant Majhi ,  Mantu K. Hudait ,  Jack T. Kavalieros ,  Ravi Pillarisetty ,  Marko Radosavljevic ,  Gilbert Dewey ,  Titash Rakshit ,  Willman Tsai

Inventor： Prashant Majhi ,  Mantu K. Hudait ,  Jack T. Kavalieros ,  Ravi Pillarisetty ,  Marko Radosavljevic ,  Gilbert Dewey ,  Titash Rakshit ,  Willman Tsai

IPC: H01L21/00

CPC classification number: H01L29/66431 ,  H01L21/28518 ,  H01L21/76802 ,  H01L21/76805 ,  H01L21/76897 ,  H01L29/152 ,  H01L29/165 ,  H01L29/41766 ,  H01L29/517 ,  H01L29/66462 ,  H01L29/7783 ,  H01L29/7848 ,  H01L29/802

Abstract: Embodiments described include straining transistor quantum well (QW) channel regions with metal source/drains, and conformal regrowth source/drains to impart a uni-axial strain in a MOS channel region. Removed portions of a channel layer may be filled with a junction material having a lattice spacing different than that of the channel material to causes a uni-axial strain in the channel, in addition to a bi-axial strain caused in the channel layer by a top barrier layer and a bottom buffer layer of the quantum well.

Abstract translation: 所描述的实施例包括具有金属源/漏极的应变晶体管量子阱（QW）沟道区，以及保形再生长源/漏极，以在MOS沟道区中赋予单轴应变。 沟道层的去除部分可以填充具有不同于沟道材料的晶格间隔的结合材料，以在通道中引起单轴应变，以及在沟道层中引起的双轴应变 顶部阻挡层和量子阱的底部缓冲层。

公开(公告)号：US20100163927A1

公开(公告)日：2010-07-01

申请号：US12319097

申请日：2008-12-30

Applicant: Ravi Pillarisetty ,  Mantu Hudait ,  Marko Radosavljevic ,  Willy Rachmady ,  Gilbert Dewey ,  Jack Kavalieros

Inventor： Ravi Pillarisetty ,  Mantu Hudait ,  Marko Radosavljevic ,  Willy Rachmady ,  Gilbert Dewey ,  Jack Kavalieros

IPC: H01L29/778 ,  H01L21/335

CPC classification number: H01L29/155 ,  H01L21/823807 ,  H01L21/823892 ,  H01L29/0653 ,  H01L29/205 ,  H01L29/207 ,  H01L29/66431 ,  H01L29/66462 ,  H01L29/66795 ,  H01L29/7831

Abstract: Embodiments of an apparatus and methods for providing three-dimensional complementary metal oxide semiconductor devices comprising modulation doped transistors are generally described herein. Other embodiments may be described and claimed.

Abstract translation: 本文通常描述用于提供包括调制掺杂晶体管的三维互补金属氧化物半导体器件的装置和方法的实施例。 可以描述和要求保护其他实施例。

公开(公告)号：US20090325350A1

公开(公告)日：2009-12-31

申请号：US12114227

申请日：2008-05-02

Applicant: Marko Radosavljevic ,  Suman Datta ,  Brian S. Doyle ,  Jack Kavalieros ,  Justin K. Brask ,  Mark L. Doczy ,  Amian Majumdar ,  Robert S. Chau

Inventor： Marko Radosavljevic ,  Suman Datta ,  Brian S. Doyle ,  Jack Kavalieros ,  Justin K. Brask ,  Mark L. Doczy ,  Amian Majumdar ,  Robert S. Chau

IPC: H01L21/762 ,  H01L21/336

CPC classification number: H01L29/41791 ,  H01L21/3141 ,  H01L23/485 ,  H01L29/66636 ,  H01L29/7843 ,  H01L29/785 ,  H01L29/78621 ,  H01L29/78681 ,  H01L29/78684 ,  H01L2029/7858 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A semiconductor device comprising a gate electrode formed on a gate dielectric layer formed on a semiconductor film. A pair of source/drain regions are formed adjacent the channel region on opposite sides of the gate electrode. The source and drain regions each comprise a semiconductor portion adjacent to and in contact with the semiconductor channel and a metal portion adjacent to and in contact with the semiconductor portion.

Abstract translation: 一种半导体器件，包括形成在形成在半导体膜上的栅极电介质层上的栅电极。 一对源极/漏极区域形成在栅电极的相对侧上的沟道区域附近。 源极和漏极区域各自包括与半导体沟道相邻并与其接触的半导体部分和与半导体部分相邻并与其接触的金属部分。

公开(公告)号：US07638169B2

公开(公告)日：2009-12-29

申请号：US11391920

申请日：2006-03-28

Applicant: Marko Radosavljevic ,  Jack T. Kavalieros ,  Amlan Majumdar ,  Suman Datta

Inventor： Marko Radosavljevic ,  Jack T. Kavalieros ,  Amlan Majumdar ,  Suman Datta

IPC: C23C16/00

CPC classification number: B82Y40/00 ,  B82Y30/00 ,  C01B32/162

Abstract: Embodiments of the invention include apparatuses and methods relating to directed carbon nanotube growth using a patterned layer. In some embodiments, the patterned layer includes an inhibitor material that directs the growth of carbon nanotubes.

Abstract translation: 本发明的实施例包括与使用图案化层的定向碳纳米管生长相关的装置和方法。 在一些实施方案中，图案化层包括引导碳纳米管生长的抑制剂材料。

公开(公告)号：US20090289245A1

公开(公告)日：2009-11-26

申请号：US11524067

申请日：2006-09-19

Applicant: Been-Yih Jin ,  Robert S. Chau ,  Brian S. Doyle ,  Marko Radosavljevic

Inventor： Been-Yih Jin ,  Robert S. Chau ,  Brian S. Doyle ,  Marko Radosavljevic

IPC: H01L29/66 ,  H01L21/336

CPC classification number: H01L29/127 ,  B82Y10/00 ,  H01L29/0665 ,  H01L29/0673 ,  H01L51/0048 ,  H01L51/0508 ,  H01L51/0512 ,  Y10S977/72 ,  Y10S977/721 ,  Y10S977/742 ,  Y10S977/858 ,  Y10S977/859

Abstract: Faceted catalytic dots are used for directing the growth of carbon nanotubes. In one example, a faceted dot is formed on a substrate for a microelectronic device. A growth promoting dopant is applied to a facet of the dot using an angled implant, and a carbon nanotube is grown on the doped facet of the dot.

Abstract translation: 方面的催化点用于指导碳纳米管的生长。 在一个示例中，在微电子器件的基板上形成刻面点。 使用成角度的植入物将生长促进掺杂剂施加到点的小平面，并且在点的掺杂面上生长碳纳米管。

公开(公告)号：US20090272965A1

公开(公告)日：2009-11-05

申请号：US12150898

申请日：2008-04-30

Applicant: Willy Rachmady ,  Marko Radosavljevic ,  Mantu K. Hudait ,  Matthew V. Metz

Inventor： Willy Rachmady ,  Marko Radosavljevic ,  Mantu K. Hudait ,  Matthew V. Metz

IPC: H01L29/12 ,  H01L21/28

CPC classification number: H01L21/0228 ,  H01L21/02181 ,  H01L21/02189 ,  H01L21/02205 ,  H01L21/28273 ,  H01L21/312 ,  H01L21/3141 ,  H01L21/31641 ,  H01L21/31645 ,  H01L29/517 ,  H01L29/78

Abstract: Embodiments of the present invention describe a method of fabricating a III-V quantum well transistor with low current leakage and high on-to-off current ratio. A hydrophobic mask having an opening is formed on a semiconductor film. The opening exposes a portion on the semiconductor film where a dielectric layer is desired to be formed. A hydrophilic surface is formed on the exposed portion of the semiconductor film. A dielectric layer is then formed on the hydrophilic surface by using an atomic layer deposition process. A metal layer is deposited on the dielectric layer.

Abstract translation: 本发明的实施例描述了一种制造具有低电流泄漏和高导通截止电流比的III-V量子阱晶体管的方法。 在半导体膜上形成具有开口的疏水性掩模。 该开口暴露出希望形成介电层的半导体膜上的一部分。 亲水表面形成在半导体膜的暴露部分上。 然后通过使用原子层沉积工艺在亲水表面上形成介电层。 金属层沉积在电介质层上。

公开(公告)号：US07342277B2

公开(公告)日：2008-03-11

申请号：US11285763

申请日：2005-11-21

Applicant: Marko Radosavljevic ,  Amlan Majumdar ,  Suman Datta ,  Justin Brask ,  Brian Doyle ,  Robert Chau

Inventor： Marko Radosavljevic ,  Amlan Majumdar ,  Suman Datta ,  Justin Brask ,  Brian Doyle ,  Robert Chau

IPC: H01L29/76

CPC classification number: G11C13/025 ,  B82Y10/00 ,  G11C2213/17 ,  H01L29/78696 ,  H01L51/0048 ,  H01L51/0541

Abstract: A transistor is described having a source electrode and a drain electrode. The transistor has at least one semiconducting carbon nanotube that is electrically coupled between the source and drain electrodes. The transistor has a gate electrode and dielectric material containing one or more quantum dots between the carbon nanotube and the gate electrode.

公开(公告)号：US07170120B2

公开(公告)日：2007-01-30

申请号：US11096984

申请日：2005-03-31

Applicant: Suman Datta ,  Marko Radosavljevic ,  Brian Doyle ,  Jack Kavalieros ,  Justin Brask ,  Amlan Majumdar ,  Robert S. Chau

Inventor： Suman Datta ,  Marko Radosavljevic ,  Brian Doyle ,  Jack Kavalieros ,  Justin Brask ,  Amlan Majumdar ,  Robert S. Chau

IPC: H01L29/76

CPC classification number: H01L51/0508 ,  B82Y10/00 ,  H01L51/0048 ,  H01L51/0052 ,  Y10S977/762

Abstract: A structure to form an energy well within a Carbon nanotube is described. The structure includes a doped semiconductor region and an undoped semiconductor region. The Carbon nanotube is between the doped semiconductor region and the undoped semiconductor region. The structure also includes a delta doped semiconductor region. The undoped semiconductor region is between the Carbon nanotube and the delta doped region. The delta doped semiconductor region is doped opposite that of the doped semiconductor region.