公开(公告)号：US20080315928A1

公开(公告)日：2008-12-25

申请号：US12114726

申请日：2008-05-02

Applicant: Khurram WAHEED ,  Mahbuba Sheba ,  Robert Bogdan Staszewski ,  Socrates Vamvakos

Inventor： Khurram WAHEED ,  Mahbuba Sheba ,  Robert Bogdan Staszewski ,  Socrates Vamvakos

IPC: H03L7/06 ,  H03M1/20

CPC classification number: H03M1/0639 ,  G04F10/005 ,  H03L7/091 ,  H03L7/0991 ,  H03L2207/50 ,  H03M1/12 ,  H04L5/0007 ,  H04L27/0014 ,  H04L27/2657 ,  H04L2027/0016 ,  H04L2027/0051 ,  H04L2027/0055 ,  H04L2027/0067 ,  H04L2027/0069 ,  H04L2027/0097

Abstract: An embodiment of the present invention provides a phase locked loop that operates on clock signals derived from an RF clock signal generated by the phase locked loop. A frequency reference input provides a reference clock. A controllable oscillator generates the RF clock signal. A phase detection circuit operates on the reference clock to provide digital phase error samples indicative of a phase difference between the reference clock and the RF clock. A dithering circuit is coupled to the reference signal and injects a short sequence dither signal into the reference signal in order to overcome quantization noise and thereby improve RMS phase-error detection for integer channels.

Abstract translation: 本发明的一个实施例提供了一种锁相环，其对由锁相环产生的RF时钟信号导出的时钟信号进行操作。 频率参考输入提供参考时钟。 可控振荡器产生RF时钟信号。 相位检测电路对参考时钟进行操作，以提供指示参考时钟和RF时钟之间的相位差的数字相位误差样本。 抖动电路耦合到参考信号，并将短序列抖动信号注入到参考信号中，以便克服量化噪声，从而改进整数信道的RMS相位误差检测。

公开(公告)号：US10008980B2

公开(公告)日：2018-06-26

申请号：US14874410

申请日：2015-10-03

Applicant: Imran Bashir ,  Robert Bogdan Staszewski

Inventor： Imran Bashir ,  Robert Bogdan Staszewski

IPC: H03B5/08 ,  H03B5/12 ,  H03L7/081 ,  H03L7/099 ,  H03L7/197

CPC classification number: H03B5/1212 ,  H03B5/1215 ,  H03B5/1218 ,  H03B5/1228 ,  H03B5/124 ,  H03B5/1265 ,  H03B5/1281 ,  H03B5/1293 ,  H03B5/1296 ,  H03J2200/10 ,  H03L7/081 ,  H03L7/0991 ,  H03L7/1976

Abstract: A novel and useful digitally controlled injection-locked RF oscillator with an auxiliary loop. The oscillator is injection locked to a time delayed version of its own resonating voltage (or its second harmonic) and its frequency is modulated by manipulating the phase and amplitude of injected current. The oscillator achieves a narrow modulation tuning range and fine step size of an LC tank based digitally controlled oscillator (DCO). The DCO first gets tuned to its center frequency by means of a conventional switched capacitor array. Frequency modulation is then achieved via a novel method of digitally controlling the phase and amplitude of injected current into the LC tank generated from its own resonating voltage. A very linear deviation from the center frequency is achieved with a much lower gain resulting in a very fine resolution DCO step size and high linearity without needing to resort to oversampled noise shaped dithering.

公开(公告)号：US09685910B2

公开(公告)日：2017-06-20

申请号：US14874421

申请日：2015-10-03

Applicant: Masoud Babaie ,  Robert Bogdan Staszewski

Inventor： Masoud Babaie ,  Robert Bogdan Staszewski

IPC: H03H7/38 ,  H03F1/02 ,  H01F27/28 ,  H03F1/56 ,  H03F3/193 ,  H03F3/21 ,  H03F3/217 ,  H01F27/29 ,  H01Q1/50 ,  H03H7/40 ,  H03F3/24

CPC classification number: H03H7/38 ,  H01F27/2823 ,  H01F27/29 ,  H01Q1/50 ,  H03F1/0205 ,  H03F1/565 ,  H03F3/193 ,  H03F3/211 ,  H03F3/2171 ,  H03F3/2176 ,  H03F3/245 ,  H03F2200/318 ,  H03F2200/451 ,  H03F2200/534 ,  H03F2200/537 ,  H03F2200/541 ,  H03F2203/21106 ,  H03F2203/21139 ,  H03H7/09 ,  H03H7/40 ,  H03H7/425 ,  H03H7/427 ,  H03H7/48

Abstract: A novel and useful transmitter (TX) architecture for ultra-low power (ULP) radios. An all-digital PLL employs a digitally controlled oscillator (DCO) having switching current sources to reduce supply voltage and power consumption without sacrificing phase noise and startup margins. It also reduces 1/f noise allowing the ADPLL after settling to reduce its sampling rate or shut it off entirely during direct DCO data modulation. A switching power amplifier integrates its matching network while operating in class-E/F2 to maximally enhance its efficiency. The transmitter has been realized in 28 nm CMOS and satisfies all metal density and other manufacturing rules. It consumes 3.6 mW/5.5 mW while delivering 0 dBm/3 dBm RF power in Bluetooth Low-Energy.

公开(公告)号：US09634610B2

公开(公告)日：2017-04-25

申请号：US14874427

申请日：2015-10-03

Applicant: Masoud Babaie ,  Robert Bogdan Staszewski

Inventor： Masoud Babaie ,  Robert Bogdan Staszewski

IPC: H03F3/60 ,  H03F1/02 ,  H01F27/28 ,  H03F1/56 ,  H03F3/193 ,  H03F3/21 ,  H03F3/217 ,  H03H7/38 ,  H01F27/29 ,  H01Q1/50 ,  H03H7/40 ,  H03F3/24

CPC classification number: H03H7/38 ,  H01F27/2823 ,  H01F27/29 ,  H01Q1/50 ,  H03F1/0205 ,  H03F1/565 ,  H03F3/193 ,  H03F3/211 ,  H03F3/2171 ,  H03F3/2176 ,  H03F3/245 ,  H03F2200/318 ,  H03F2200/451 ,  H03F2200/534 ,  H03F2200/537 ,  H03F2200/541 ,  H03F2203/21106 ,  H03F2203/21139 ,  H03H7/09 ,  H03H7/40 ,  H03H7/425 ,  H03H7/427 ,  H03H7/48

Abstract: A novel and useful fully integrated switched-mode wideband 60 GHz power amplifier architecture. Using an appropriate second-harmonic termination of its output matching network, the required systematic peak current of the final stage is reduced such that the PA functions as a class-E/F2 switched-mode PA at saturation. In addition, low/moderate magnetic coupling factor transformers in the intermediate stages enable the PA to reach a high power added efficiency (PAE) and bandwidth product. Transformers of low/moderate coupling are also utilized in the preliminary stages of the PA to improve the overall bandwidth. In addition, the PA exploits the different behavior of the output impedance matching network for differential mode (DM) and common mode (CM) excitations. The PA is also stabilized against the combination of DM and CM oscillation modes. The PA also provides a technique to stabilize transformer-based mm-wave amplifiers against various modes of undesired oscillations.

公开(公告)号：US09401677B2

公开(公告)日：2016-07-26

申请号：US14831119

申请日：2015-08-20

Applicant: Augusto Ronchini Ximenes ,  Robert Bogdan Staszewski

Inventor： Augusto Ronchini Ximenes ,  Robert Bogdan Staszewski

IPC: H03B5/12 ,  H03B1/00 ,  H03K3/015 ,  G04F10/00 ,  H03L7/08 ,  H03M1/00 ,  H03L7/093 ,  H03M1/20 ,  H03L7/089 ,  H03L7/197 ,  H03K3/03

CPC classification number: H03B5/1265 ,  G04F10/005 ,  H03B1/00 ,  H03B5/1215 ,  H03B5/1228 ,  H03B5/1296 ,  H03J2200/10 ,  H03K3/015 ,  H03K3/0315 ,  H03L7/0802 ,  H03L7/0893 ,  H03L7/093 ,  H03L7/1976 ,  H03L2207/50 ,  H03M1/002 ,  H03M1/201

Abstract: A novel and useful LC-tank digitally controlled oscillator (DCO) incorporating a split transformer configuration. The LC-tank oscillator exhibits a significant reduction in area such that it is comparable in size to conventional ring oscillators (ROs) while still retaining its salient features of excellent phase noise and low sensitivity to supply variations. The oscillator incorporates an ultra-compact split transformer topology that is less susceptible to common-mode electromagnetic interference than regular high-Q LC tanks which is highly desirable in SoC environments. The oscillator, together with a novel dc-coupled buffer, can be incorporated within a wide range of circuit applications, including clock generators and an all-digital phase-locked loop (ADPLL) intended for wireline applications.

Abstract translation: 一种新颖有用的LC-tank数字控制振荡器（DCO），其包含分离变压器配置。 LC-tank振荡器显示出显着的面积减小，使得它在尺寸上与常规的环形振荡器（RO）相当，同时仍然保持其显着的相位噪声特征以及对供应变化的低灵敏度。 该振荡器包含一个超紧凑型分离式变压器拓扑，它比常规高Q液相色谱箱容易受到共模电磁干扰的影响，这在SoC环境中是非常需要的。 该振荡器与一个新颖的直流耦合缓冲器可以并入广泛的电路应用中，包括时钟发生器和用于有线应用的全数字锁相环（ADPLL）。

公开(公告)号：US20160099720A1

公开(公告)日：2016-04-07

申请号：US14874410

申请日：2015-10-03

Applicant: Imran Bashir ,  Robert Bogdan Staszewski

Inventor： Imran Bashir ,  Robert Bogdan Staszewski

IPC: H03L7/099 ,  H03L7/081 ,  H03B5/12

CPC classification number: H03B5/1212 ,  H03B5/1215 ,  H03B5/1218 ,  H03B5/1228 ,  H03B5/124 ,  H03B5/1265 ,  H03B5/1281 ,  H03B5/1293 ,  H03B5/1296 ,  H03J2200/10 ,  H03L7/081 ,  H03L7/0991 ,  H03L7/1976

Abstract: A novel and useful digitally controlled injection-locked RF oscillator with an auxiliary loop. The oscillator is injection locked to a time delayed version of its own resonating voltage (or its second harmonic) and its frequency is modulated by manipulating the phase and amplitude of injected current. The oscillator achieves a narrow modulation tuning range and fine step size of an LC tank based digitally controlled oscillator (DCO). The DCO first gets tuned to its center frequency by means of a conventional switched capacitor array. Frequency modulation is then achieved via a novel method of digitally controlling the phase and amplitude of injected current into the LC tank generated from its own resonating voltage. A very linear deviation from the center frequency is achieved with a much lower gain resulting in a very fine resolution DCO step size and high linearity without needing to resort to oversampled noise shaped dithering.

Abstract translation: 一种具有辅助回路的新颖有用的数字控制注入锁定RF振荡器。 振荡器被注入锁定到其自己的谐振电压（或其二次谐波）的时间延迟版本，并且通过操纵注入电流的相位和幅度来调制其频率。 该振荡器实现了基于LC槽的数字控制振荡器（DCO）的窄调制调谐范围和精细步长。 DCO首先通过传统的开关电容器阵列调谐到其中心频率。 然后通过数字控制从其自己的谐振电压产生的进入LC箱的注入电流的相位和幅度的新颖方法来实现频率调制。 实现了与中心频率非常线性的偏差，具有更低的增益，导致非常精细的分辨率DCO步长和高线性度，而不需要采用过采样噪声形状的抖动。

公开(公告)号：US20160056825A1

公开(公告)日：2016-02-25

申请号：US14831781

申请日：2015-08-20

Applicant: Gerasimos S. Vlachogiannakis ,  Augusto Ronchini Ximenes ,  Robert Bogdan Staszewski

Inventor： Gerasimos S. Vlachogiannakis ,  Augusto Ronchini Ximenes ,  Robert Bogdan Staszewski

IPC: H03L7/08 ,  G04F10/00 ,  H03M1/00

CPC classification number: H03B5/1265 ,  G04F10/005 ,  H03B1/00 ,  H03B5/1215 ,  H03B5/1228 ,  H03B5/1296 ,  H03J2200/10 ,  H03K3/015 ,  H03K3/0315 ,  H03L7/0802 ,  H03L7/0893 ,  H03L7/093 ,  H03L7/1976 ,  H03L2207/50 ,  H03M1/002 ,  H03M1/201

Abstract: A novel and useful look-ahead time to digital converter (TDC) that is applied to an all digital phase locked loop (ADPLL) as the fractional phase error detector. The deterministic nature of the phase error during frequency/phase lock is exploited to achieve a reduction in power consumption of the TDC. The look-ahead TDC circuit is used to construct a cyclic DTC-TDC pair which functions to reduce fractional spurs of the output spectrum in near-integer channels by randomly rotating the cyclic DTC-TDC structure so that it starts from a different point every reference clock thereby averaging out the mismatch of the elements. Associated rotation and dithering methods are also presented. The ADPLL is achieved using the look-ahead TDC and/or cyclic DTC-TDC pair circuit.

Abstract translation: 数字转换器（TDC）的新颖有用的超前时间，适用于全数字锁相环（ADPLL）作为分数相位误差检测器。 利用频率/锁相期间相位误差的确定性来实现TDC功耗的降低。 先行TDC电路用于构造循环DTC-TDC对，其通过随机旋转循环DTC-TDC结构来减少近整数通道中的输出频谱的分数杂散，使其从每个参考的不同点开始 从而平均化元件的不匹配。 还提出了相关的旋转和抖动方法。 使用前瞻TDC和/或循环DTC-TDC对电路来实现ADPLL。

公开(公告)号：US09207646B2

公开(公告)日：2015-12-08

申请号：US13610842

申请日：2012-09-11

Applicant: Chi-Hsueh Wang ,  Robert Bogdan Staszewski ,  Yi-Hsien Cho

Inventor： Chi-Hsueh Wang ,  Robert Bogdan Staszewski ,  Yi-Hsien Cho

IPC: G04F10/06 ,  G04F10/00

CPC classification number: G04F10/005

Abstract: A method of estimating gain of a time-to-digital converter (TDC) includes: capturing a TDC output sample; calculating a gradient in response to the TDC output sample; and adjusting a TDC normalizing gain based on the calculating step. Another method of calibrating gain of a TDC includes: capturing a phase error which is derived from a TDC output sample, a reference phase and a variable phase; calculating a gradient in response to the phase error; and adjusting a TDC normalizing gain based on the calculating step.

Abstract translation: 一种估计时间 - 数字转换器（TDC）的增益的方法包括：捕获TDC输出样本; 计算响应于TDC输出样本的梯度; 以及基于所述计算步骤调整TDC归一化增益。 校准TDC增益的另一种方法包括：捕获从TDC输出样本，参考相位和可变相位导出的相位误差; 计算响应于相位误差的梯度; 以及基于所述计算步骤调整TDC归一化增益。

公开(公告)号：US08766719B2

公开(公告)日：2014-07-01

申请号：US13484268

申请日：2012-05-30

Applicant: Jie-Wei Lai ,  Meng-Hsiung Hung ,  Robert Bogdan Staszewski

Inventor： Jie-Wei Lai ,  Meng-Hsiung Hung ,  Robert Bogdan Staszewski

IPC: H03F1/00

CPC classification number: H03F3/68 ,  H03F3/193 ,  H03F3/211 ,  H03F3/2171 ,  H03F3/2176 ,  H03F3/2178

Abstract: A digitally-controlled power amplifier (DPA) with bandpass filtering includes a radio-frequency (RF) clock input, an amplitude control word (ACW) input, and a plurality of DPA cells. The RF clock input is arranged for receiving an RF clock. The ACW input is arranged for receiving a digital ACW signal. The DPA cells are coupled to the RF clock and the digital ACW signal, wherein at least one of the DPA cells is gradually turned on and off in response to at least one bit of the digital ACW signal.

Abstract translation: 具有带通滤波的数字控制功率放大器（DPA）包括射频（RF）时钟输入，幅度控制字（ACW）输入和多个DPA信元。 RF时钟输入被布置用于接收RF时钟。 ACW输入被安排用于接收数字ACW信号。 DPA单元耦合到RF时钟和数字ACW信号，其中响应于数字ACW信号的至少一位，DPA单元中的至少一个逐渐导通和截止。

公开(公告)号：US08669890B2

公开(公告)日：2014-03-11

申请号：US13610827

申请日：2012-09-11

Applicant: Chi-Hsueh Wang ,  Robert Bogdan Staszewski ,  Yi-Hsien Cho

Inventor： Chi-Hsueh Wang ,  Robert Bogdan Staszewski ,  Yi-Hsien Cho

IPC: H03M1/06

CPC classification number: G04F10/005

Abstract: A method of estimating mismatches of a time-to-digital converter (TDC) includes: capturing phase error samples; calculating difference between the phase error samples and an expected value of the phase error samples; and adjusting correction gain of the TDC based on the calculating step. Another method of estimating mismatches of a TDC includes: capturing TDC output code samples; storing a plurality of accumulation values corresponding to different TDC values respectively, wherein each accumulation value records a number of times a TDC value is carried by the TDC output code samples; calculating a desired value based on the accumulation values; calculating difference between the accumulation values and the desired value; and adjusting correction gain of the TDC based on the calculating step.

Abstract translation: 一种估计时间 - 数字转换器（TDC）的不匹配的方法包括：捕获相位误差样本; 计算相位误差样本与相位误差样本的期望值之间的差异; 以及基于所述计算步骤调整所述TDC的校正增益。 估计TDC不匹配的另一种方法包括：捕获TDC输出码样本; 分别存储对应于不同TDC值的多个累加值，其中每个累积值记录TDC输出代码样本携带TDC值的次数; 基于累积值计算期望值; 计算积累值和期望值之间的差异; 以及基于所述计算步骤调整所述TDC的校正增益。