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42 条记录 (耗时 0.034 秒)

    OPERATING METHODS OF NONVOLATILE MEMORY DEVICES
    34.
    发明申请
    OPERATING METHODS OF NONVOLATILE MEMORY DEVICES 审中-公开
    非易失性存储器件的操作方法

    公开(公告)号：US20150348636A1

    公开(公告)日：2015-12-03

    申请号：US14820703

    申请日：2015-08-07

    申请人： Byeong-in Choe ,  Jaehoon JANG ,  Kihyun KIM ,  Sunil SHIM ,  Woonkyung Lee

    发明人： Byeong-in Choe ,  Jaehoon JANG ,  Kihyun KIM ,  Sunil SHIM ,  Woonkyung Lee

    IPC分类号： G11C16/14 ,  G11C16/04

    CPC分类号： G11C16/14 ,  G11C7/14 ,  G11C16/0483 ,  G11C16/10 ,  G11C16/16 ,  G11C16/30 ,  H01L27/11582 ,  H01L29/7926

    摘要： Disclosed are methods of operating a nonvolatile memory device which includes a substrate and a plurality of cell strings provided on the substrate, each cell string including a plurality of memory cells stacked in a direction perpendicular to the substrate. The methods may include applying a word line erase voltage to word lines connected to memory cells of the cell strings; floating ground selection lines connected to ground selection transistors of the cell strings and string selection lines connected to string selection transistors of the plurality of cell strings; applying a ground voltage to at least one lower dummy word line connected to at least one lower dummy memory cell between memory cells and a ground selection transistor in each of the plurality of cell strings; applying an erase voltage to the substrate; and floating the at least one lower dummy word line after applying of the erase voltage.

    摘要翻译： 公开了一种非易失性存储器件的操作方法，其包括衬底和设置在衬底上的多个单元串，每个单元串包括沿垂直于衬底的方向堆叠的多个存储单元。 所述方法可以包括将字线擦除电压施加到连接到所述单元串的存储单元的字线; 连接到单元串的地选择晶体管的浮动接地选择线和连接到多个单元串的串选择晶体管的串选择线; 将至少一个连接到所述多个单元串中的每一个的存储单元之间的至少一个下部虚设存储单元和所述多个单元串中的接地选择晶体管的下虚拟字线施加接地电压; 向基板施加擦除电压; 并且在施加擦除电压之后浮置所述至少一个下部虚拟字线。

    Nonvolatile memory device and method of making the same
    35.
    发明授权
    Nonvolatile memory device and method of making the same 有权
    非易失存储器件及其制造方法

    公开(公告)号：US08916926B2

    公开(公告)日：2014-12-23

    申请号：US13310407

    申请日：2011-12-02

    申请人： Byeong-In Choe ,  Sunil Shim ,  Sung-Hwan Jang ,  Woonkyung Lee ,  Jaehoon Jang

    发明人： Byeong-In Choe ,  Sunil Shim ,  Sung-Hwan Jang ,  Woonkyung Lee ,  Jaehoon Jang

    IPC分类号： H01L27/115 ,  G11C16/04 ,  H01L29/792

    CPC分类号： H01L27/1157 ,  G11C16/0483 ,  H01L27/11582 ,  H01L29/7926

    摘要： A nonvolatile memory device includes a substrate, a structure including a stack of alternately disposed layers of conductive and insulation materials disposed on the substrate, a plurality of pillars extending through the structure in a direction perpendicular to the substrate and into contact with the substrate, and information storage films interposed between the layers of conductive material and the pillars. In one embodiment, upper portions of the pillars located at the same level as an upper layer of the conductive material have structures that are different from lower portions of the pillars. In another embodiment, or in addition, upper string selection transistors constituted by portions of the pillars at the level of an upper layer of the conductive material are programmed differently from lower string selection transistors.

    摘要翻译： 非易失性存储器件包括衬底，包括布置在衬底上的交替设置的导电和绝缘材料层的堆叠的结构，沿与衬底垂直的方向延伸并与衬底接触的多个柱，以及 介于导电材料层和支柱之间的信息存储膜。 在一个实施例中，位于与导电材料的上层相同水平的柱的上部具有与柱的下部不同的结构。 在另一个实施例中，或者另外，由导电材料的上层的电平的柱的部分构成的上部串选择晶体管被编程为与下部串选择晶体管不同。

    SEMICONDUCTOR DEVICES AND METHODS OF FABRICATING THE SAME
    36.
    发明申请
    SEMICONDUCTOR DEVICES AND METHODS OF FABRICATING THE SAME 审中-公开
    半导体器件及其制造方法

    公开(公告)号：US20130020647A1

    公开(公告)日：2013-01-24

    申请号：US13540799

    申请日：2012-07-03

    申请人： Sung-Min HWANG ,  In-Wook Oh ,  Woonkyung Lee ,  Aaron Park ,  Hoosung Cho

    发明人： Sung-Min HWANG ,  In-Wook Oh ,  Woonkyung Lee ,  Aaron Park ,  Hoosung Cho

    IPC分类号： H01L29/78 ,  H01L23/498

    CPC分类号： H01L27/11582 ,  H01L27/11565 ,  H01L27/11573 ,  H01L27/11575

    摘要： Semiconductor devices are provided. The semiconductor device includes conductive patterns vertically stacked on a substrate to be spaced apart from each other, and pad patterns electrically connected to respective ones of the conductive patterns. Each of the pad patterns includes a flat portion extending from an end of the conductive pattern in a first direction parallel with the substrate and a landing sidewall portion upwardly extending from an end of the flat portion. A width of a portion of the landing sidewall portion in a second direction parallel with the substrate and perpendicular to the first direction is less than a width of the flat portion in the second direction. The related methods are also provided.

    摘要翻译： 提供半导体器件。 半导体器件包括垂直堆叠在基板上以彼此间隔开的导电图案，以及电连接到相应导电图案的焊盘图案。 每个焊盘图案包括从平行于基板的第一方向从导电图案的端部延伸的平坦部分和从平坦部分的端部向上延伸的着陆侧壁部分。 着陆侧壁部的与基板平行且垂直于第一方向的第二方向的一部分的宽度小于第二方向上的平坦部的宽度。 还提供了相关方法。

    OPERATING METHOD OF NONVOLATILE MEMORY DEVICE
    37.
    发明申请
    OPERATING METHOD OF NONVOLATILE MEMORY DEVICE 有权
    非易失性存储器件的操作方法

    公开(公告)号：US20120195125A1

    公开(公告)日：2012-08-02

    申请号：US13315523

    申请日：2011-12-09

    申请人： BYEONG-IN CHOE ,  Sunil Shim ,  Woonkyung Lee ,  Jaehoon Jang

    发明人： BYEONG-IN CHOE ,  Sunil Shim ,  Woonkyung Lee ,  Jaehoon Jang

    IPC分类号： G11C16/10 ,  G11C16/04

    CPC分类号： G11C16/10 ,  G11C16/0483 ,  G11C16/3459 ,  H01L27/11582

    摘要： Disclosed is an operating method of a nonvolatile memory device, which includes programming the first selection transistors of the plurality of cell strings and programming the plurality of memory cells of the plurality of cell strings. The programming the first selection transistors comprises supplying a first voltage to a first bit line connected with a first selection transistor to be programmed and a different second voltage to a second bit line connected to a first selection transistor to be program inhibited; turning on the second selection transistors of the plurality of cell strings, and supplying a first program voltage to a selected first selection line among a plurality of first selection lines connected with the first selection transistors and a third voltage to an unselected first selection line among the plurality of first selection lines.

    摘要翻译： 公开了一种非易失性存储器件的操作方法，其包括编程多个单元串中的第一选择晶体管并对多个单元串中的多个存储单元进行编程。 对第一选择晶体管进行编程包括将第一电压提供给与待编程的第一选择晶体管连接的第一位线，以及将不同的第二电压提供给连接到第一选择晶体管的第二位线以被禁止编程; 接通多个单元串中的第二选择晶体管，并将第一编程电压提供给与第一选择晶体管连接的多个第一选择线中的所选择的第一选择线，以及将第三电压提供给未选择的第一选择线 多个第一选择线。

    NONVOLATILE MEMORY DEVICE AND METHOD OF MAKING THE SAME
    38.
    发明申请
    NONVOLATILE MEMORY DEVICE AND METHOD OF MAKING THE SAME 有权
    非易失存储器件及其制造方法

    公开(公告)号：US20120140562A1

    公开(公告)日：2012-06-07

    申请号：US13310407

    申请日：2011-12-02

    申请人： Byeong-In Choe ,  Sunil Shim ,  Sung-Hwan Jang ,  Woonkyung Lee ,  Jaehoon Jang

    发明人： Byeong-In Choe ,  Sunil Shim ,  Sung-Hwan Jang ,  Woonkyung Lee ,  Jaehoon Jang

    IPC分类号： G11C16/04 ,  H01L29/78

    CPC分类号： H01L27/1157 ,  G11C16/0483 ,  H01L27/11582 ,  H01L29/7926

    摘要： A nonvolatile memory device includes a substrate, a structure including a stack of alternately disposed layers of conductive and insulation materials disposed on the substrate, a plurality of pillars extending through the structure in a direction perpendicular to the substrate and into contact with the substrate, and information storage films interposed between the layers of conductive material and the pillars. In one embodiment, upper portions of the pillars located at the same level as an upper layer of the conductive material have structures that are different from lower portions of the pillars. In another embodiment, or in addition, upper string selection transistors constituted by portions of the pillars at the level of an upper layer of the conductive material are programmed differently from lower string selection transistors.

    摘要翻译： 非易失性存储器件包括衬底，包括布置在衬底上的交替设置的导电和绝缘材料层的堆叠的结构，沿与衬底垂直的方向延伸并与衬底接触的多个柱，以及 介于导电材料层和支柱之间的信息存储膜。 在一个实施例中，位于与导电材料的上层相同水平的柱的上部具有与柱的下部不同的结构。 在另一个实施例中，或者另外，由导电材料的上层的电平的柱的部分构成的上部串选择晶体管被编程为与下部串选择晶体管不同。

    Nonvolatile Memory Devices, Erasing Methods Thereof and Memory Systems Including the Same
    39.
    发明申请
    Nonvolatile Memory Devices, Erasing Methods Thereof and Memory Systems Including the Same 有权
    非易失性存储器件，其擦除方法和包括其的存储器系统

    公开(公告)号：US20120120740A1

    公开(公告)日：2012-05-17

    申请号：US13295335

    申请日：2011-11-14

    申请人： Sunil Shim ,  Jaehoon Jang ,  Jungdal Choi ,  Woonkyung Lee ,  Kihyun Kim

    发明人： Sunil Shim ,  Jaehoon Jang ,  Jungdal Choi ,  Woonkyung Lee ,  Kihyun Kim

    IPC分类号： G11C7/00

    CPC分类号： G11C16/14 ,  G11C16/0483 ,  G11C16/16 ,  G11C16/30 ,  H01L27/11582 ,  H01L29/7926

    摘要： Disclosed are erase methods for a memory device which includes a substrate and a plurality of cell strings provided on the substrate, each cell string including a plurality of cell transistors stacked in a direction perpendicular to the substrate. The erase method includes applying a ground voltage to a ground selection line connected with ground selection transistors of the plurality of cell strings; applying a ground voltage to string selection lines connected with selection transistors of the plurality of cell strings; applying a word line erase voltage to word lines connected with memory cells of the plurality of cell strings; applying an erase voltage to the substrate; controlling a voltage of the ground selection line in response to applying of the erase voltage; and controlling voltages of the string selection lines in response to the applying of the erase voltage.

    摘要翻译： 公开了一种存储器件的擦除方法，其包括衬底和设置在衬底上的多个单元串，每个单元串包括沿垂直于衬底的方向堆叠的多个单元晶体管。 所述擦除方法包括将地电压施加到与所述多个单元串的接地选择晶体管相连的接地选择线; 对与所述多个单元串的选择晶体管连接的串选择线施加接地电压; 对与多个单元串的存储单元相连的字线施加字线擦除电压; 向基板施加擦除电压; 响应于施加所述擦除电压来控制所述接地选择线的电压; 以及响应于施加所述擦除电压来控制所述串选择线的电压。