公开(公告)号：US06995061B2

公开(公告)日：2006-02-07

申请号：US10779607

申请日：2004-02-18

Applicant: Ching-Nan Hsiao ,  Chi-Hui Lin ,  Ying-Cheng Chuang

Inventor： Ching-Nan Hsiao ,  Chi-Hui Lin ,  Ying-Cheng Chuang

IPC: H01L21/336

CPC classification number: H01L21/28273 ,  H01L29/66825 ,  H01L29/7887

Abstract: The present invention discloses a multi-bit stacked-type non-volatile memory having a spacer-shaped floating gate and a manufacturing method thereof. The manufacturing method includes forming a patterned dielectric layer containing arsenic on a semiconductor substrate, wherein the patterned dielectric layer defines an opening as an active area. A dielectric spacer is formed on a side wall of the patterned dielectric layer and a gate dielectric layer is formed on the semiconductor substrate. A source/drain region is formed by thermal driving method making arsenic diffusion from the patterned dielectric layer into the semiconductor substrate. A spacer-shaped floating gate is formed on the side wall of the dielectric spacer and the gate dielectric layer. An interlayer dielectric layer is formed on the spacer-shaped floating gate. A control gate is formed on the interlayer dielectric layer and fills the opening of the active area.

公开(公告)号：US06916715B2

公开(公告)日：2005-07-12

申请号：US10694155

申请日：2003-10-27

Applicant: Ching-Nan Hsiao ,  Chi-Hui Lin ,  Chung-Lin Huang ,  Ying-Cheng Chuang

Inventor： Ching-Nan Hsiao ,  Chi-Hui Lin ,  Chung-Lin Huang ,  Ying-Cheng Chuang

IPC: H01L21/336 ,  H01L21/8234 ,  H01L21/8246 ,  H01L27/115 ,  H01L27/148

CPC classification number: H01L27/11568 ,  H01L27/115

Abstract: A method for fabricating a vertical nitride read-only memory (NROM) cell. A substrate having at least one trench is provided. A spacer is formed over the sidewall of the trench. Subsequently, ion implantation is performed on the substrate using the spacer as a mask to form doping areas as bit lines in the substrate near its surface and the bottom of the trench. Bit line oxides are formed over each of the doping areas. After the spacer is removed, a conformable insulating layer as gate dielectric is deposited on the sidewall of the trench and the surface of the bit line oxide. Finally, a conductive layer as a word line is deposited over the insulating layer and fills in the trench.

Abstract translation: 一种用于制造垂直氮化物只读存储器（NROM）单元的方法。 提供具有至少一个沟槽的衬底。 间隔件形成在沟槽的侧壁上。 随后，使用间隔物作为掩模在衬底上进行离子注入，以在沟槽的表面和底部附近的衬底中形成作为位线的掺杂区域。 在每个掺杂区域上形成位线氧化物。 在移除间隔物之后，在沟槽的侧壁和位线氧化物的表面上沉积作为栅极电介质的适形绝缘层。 最后，作为字线的导电层沉积在绝缘层上并填充在沟槽中。

公开(公告)号：US06893919B2

公开(公告)日：2005-05-17

申请号：US10810740

申请日：2004-03-26

Applicant: Ying-Cheng Chuang ,  Chung-Lin Huang

Inventor： Ying-Cheng Chuang ,  Chung-Lin Huang

IPC: H01L21/8247 ,  H01L27/115 ,  H01L21/336

CPC classification number: H01L21/28273 ,  H01L27/115 ,  H01L27/11521

Abstract: A floating gate and a fabricating method of the same. A semiconductor substrate is provided. A gate dielectric layer and a conducting layer are sequentially formed on the semiconductor substrate. A patterned hard mask layer having an opening is formed on the conducting layer, wherein a portion of the conducting layer is exposed through the opening. A spacer is formed on the sidewall of the opening. The patterned hard mask layer is removed. A conducting spacer is formed on the sidewall of the spacer. The exposed conducting layer and the exposed gate dielectric layer are sequentially removed.

公开(公告)号：US20050087823A1

公开(公告)日：2005-04-28

申请号：US10994018

申请日：2004-11-19

Applicant: Ching-Nan Hsiao ,  Chao-Sung Lai ,  Yung-Meng Huang ,  Ying-Cheng Chuang

Inventor： Ching-Nan Hsiao ,  Chao-Sung Lai ,  Yung-Meng Huang ,  Ying-Cheng Chuang

IPC: H01L21/28 ,  H01L21/336 ,  H01L21/8238 ,  H01L21/8242 ,  H01L21/8246 ,  H01L27/115 ,  H01L29/76 ,  H01L29/792

CPC classification number: H01L27/11568 ,  H01L27/115 ,  H01L29/40117 ,  H01L29/66833 ,  H01L29/7923

Abstract: A read-only memory cell (ROM) and a fabrication method thereof. The cell comprises a substrate, a plurality of bit lines, a plurality of bit line oxides, a gate dielectric layer and a word line. The bit lines are formed near the surface of the substrate. The bit line oxides are disposed over the bit lines. The gate dielectric layer is disposed over the substrate between the bit lines and further comprises a silicon-rich oxide layer. The word line is disposed over the bit line oxides and the gate dielectric layer.

Abstract translation: 只读存储单元（ROM）及其制造方法。 电池包括衬底，多个位线，多个位线氧化物，栅极电介质层和字线。 在基板的表面附近形成位线。 位线氧化物位于位线之上。 栅介电层设置在位线之间的衬底上，并且还包括富硅氧化物层。 字线设置在位线氧化物和栅极电介质层之上。

公开(公告)号：US06847068B2

公开(公告)日：2005-01-25

申请号：US10441801

申请日：2003-05-19

Applicant: Ying-Cheng Chuang ,  Chung-Lin Huang ,  Chi-Hui Lin

Inventor： Ying-Cheng Chuang ,  Chung-Lin Huang ,  Chi-Hui Lin

IPC: H01L21/28 ,  H01L29/423 ,  H01L21/8242

CPC classification number: H01L29/42324 ,  H01L21/28273

Abstract: A floating gate with multiple tips and a fabrication method thereof. A semiconductor substrate is provided, on which a patterned hard mask layer is formed, wherein the patterned hard mask layer has an opening. A gate dielectric layer and a first conducting layer with a first predetermined thickness are formed on the bottom of the opening. A spacer is formed on the sidewall of the opening. A conducting spacer is formed on the sidewall of the spacer. The first conducting layer is etched to a second predetermined thickness. A multi-tip floating gate is provided by the first conducting layer and the conducting spacer. A protecting layer is formed in the opening. The patterned hard mask layer, the gate dielectric layer, a portion of the protecting layer, and a portion of the first spacer are etched to expose the surface of the first conducting layer.

公开(公告)号：US08901631B2

公开(公告)日：2014-12-02

申请号：US13792231

申请日：2013-03-11

Applicant: Sheng-Wei Yang ,  Ying-Cheng Chuang ,  Shyam Surthi

Inventor： Sheng-Wei Yang ,  Ying-Cheng Chuang ,  Shyam Surthi

IPC: H01L29/94 ,  H01L29/06 ,  H01L21/765

CPC classification number: H01L21/765 ,  H01L21/265 ,  H01L21/32055 ,  H01L21/324 ,  H01L21/76897 ,  H01L21/823481 ,  H01L27/088 ,  H01L27/1052 ,  H01L27/10876 ,  H01L29/0607 ,  H01L29/407 ,  H01L29/66666 ,  H01L29/78 ,  H01L29/7827

Abstract: Provided is a method for fabricating a semiconductor device, including the following steps. A substrate having a plurality of pillars is provided, wherein a plurality of trenches are formed around each pillar. A doped region is formed in the substrate and below each pillar. The doped region below each trench is removed to form an opening such that the doped regions below the adjacent pillars are separated from each other. A shielding layer is formed in each opening.

Abstract translation: 提供一种制造半导体器件的方法，包括以下步骤。 提供具有多个支柱的基板，其中围绕每个支柱形成多个沟槽。 在衬底中并在每个柱下方形成掺杂区域。 去除每个沟槽下方的掺杂区域以形成开口，使得相邻支柱之下的掺杂区域彼此分离。 在每个开口中形成屏蔽层。

公开(公告)号：US08426925B2

公开(公告)日：2013-04-23

申请号：US12945536

申请日：2010-11-12

Applicant: Ying Cheng Chuang ,  Ping Cheng Hsu ,  Sheng Wei Yang ,  Ming Cheng Chang ,  Hung Ming Tsai

Inventor： Ying Cheng Chuang ,  Ping Cheng Hsu ,  Sheng Wei Yang ,  Ming Cheng Chang ,  Hung Ming Tsai

IPC: H01L29/76 ,  H01L29/94 ,  H01L31/062 ,  H01L31/113 ,  H01L31/119

CPC classification number: H01L21/76224 ,  H01L27/10876 ,  H01L27/10891

Abstract: A memory device includes a plurality of isolations and trench fillers arranged in an alternating manner in a direction, a plurality of mesa structures between the isolations and trench fillers, and a plurality of word lines each overlying a side surface of the respective mesa. In one embodiment of the present invention, the width measured in the direction of the trench filler is smaller than that of the isolation, each mesa structure includes at least one paired source/drain regions and at least one channel base region corresponding to the paired source/drain regions, and each of the word lines is on a side surface of the mesa structure, adjacent the respective isolation, and is arranged adjacent the channel base region.

Abstract translation: 存储器件包括多个隔离件和沟槽填料，沿方向交替排列，隔离件和沟槽填料之间的多个台面结构，以及各自覆盖相应台面的侧表面的多个字线。 在本发明的一个实施例中，在沟槽填料的方向上测量的宽度小于隔离层的宽度，每个台面结构包括至少一个成对的源极/漏极区域和对应于配对源极的至少一个沟道基极区域 /漏极区域，并且每个字线在台面结构的侧表面上，与相应的隔离相邻，并且被布置为与通道基底区域相邻。

公开(公告)号：US20120108047A1

公开(公告)日：2012-05-03

申请号：US12917339

申请日：2010-11-01

Applicant: Ying-Cheng Chuang ,  Hung-Ming Tsai ,  Sheng-Wei Yang ,  Ping-Cheng Hsu ,  Ming-Cheng Chang

Inventor： Ying-Cheng Chuang ,  Hung-Ming Tsai ,  Sheng-Wei Yang ,  Ping-Cheng Hsu ,  Ming-Cheng Chang

IPC: H01L21/768 ,  H01L21/28

CPC classification number: H01L27/10876 ,  H01L21/28531 ,  H01L21/76897 ,  H01L27/10855 ,  H01L27/10888

Abstract: A method of forming a conductive contact includes forming a structure comprising an upper surface joining with a sidewall surface. The sidewall surface contains elemental-form silicon. Silicon is epitaxially grown from the sidewall surface. Dielectric material is formed over the upper surface and the epitaxially-grown silicon. A conductive contact is formed through the dielectric material to conductively connect with the upper surface.

Abstract translation: 形成导电接触的方法包括形成包括与侧壁表面接合的上表面的结构。 侧壁表面含有元素型硅。 硅从侧壁表面外延生长。 电介质材料形成在上表面和外延生长的硅上。 通过电介质材料形成导电接触，以与上表面导电连接。

公开(公告)号：US20070063260A1

公开(公告)日：2007-03-22

申请号：US11603771

申请日：2006-11-22

Applicant: Ying-Cheng Chuang ,  Chung-Lin Huang ,  Chi-Hui Lin

Inventor： Ying-Cheng Chuang ,  Chung-Lin Huang ,  Chi-Hui Lin

IPC: H01L29/788

CPC classification number: H01L27/11521 ,  H01L21/28273 ,  H01L29/42324 ,  H01L29/7881

Abstract: A floating gate and fabrication method thereof. A semiconductor substrate is provided, on which an oxide layer, a first conducting layer, and a patterned hard mask layer having an opening are sequentially formed. A spacer is formed on the sidewall of the opening. A second conducting layer is formed on the hard mask layer. The second conducting layer is planarized to expose the surface of the patterned hard mask layer. The surface of the second conducting layer is oxidized to form an oxide layer. The patterned hard mask layer and the oxide layer and the first conducting layer underlying the patterned hard mask layer are removed.

Abstract translation: 浮栅及其制造方法。 提供了半导体衬底，其上依次形成有氧化物层，第一导电层和具有开口的图案化硬掩模层。 间隔件形成在开口的侧壁上。 在硬掩模层上形成第二导电层。 将第二导电层平坦化以暴露图案化硬掩模层的表面。 第二导电层的表面被氧化形成氧化物层。 图案化的硬掩模层和氧化物层以及图案化的硬掩模层下面的第一导电层被去除。

公开(公告)号：US07022573B2

公开(公告)日：2006-04-04

申请号：US10884701

申请日：2004-07-02

Applicant: Ching-Nan Hsiao ,  Ying-Cheng Chuang ,  Chi-Hui Lin

Inventor： Ching-Nan Hsiao ,  Ying-Cheng Chuang ,  Chi-Hui Lin

IPC: H01L21/336

CPC classification number: H01L27/11556 ,  H01L27/115 ,  H01L29/42336 ,  H01L29/7881

Abstract: A stacked gate vertical flash memory and a fabrication method thereof. The stacked gate vertical flash memory comprises a semiconductor substrate with a trench, a source conducting layer formed on the bottom of the trench, an insulating layer formed on the source conducting layer, a gate dielectric layer formed on a sidewall of the trench, a conducting spacer covering the gate dielectric layer as a floating gate, an inter-gate dielectric layer covering the conducting spacer, and a control gate conducting layer filled in the trench.

Abstract translation: 堆叠式门垂直闪存及其制造方法。 层叠栅极垂直闪速存储器包括具有沟槽的半导体衬底，形成在沟槽底部的源极导电层，形成在源极导电层上的绝缘层，形成在沟槽侧壁上的栅极电介质层，导电层 覆盖作为浮动栅极的栅极介电层的隔板，覆盖导电间隔物的栅极间介电层和填充在沟槽中的控制栅极导电层。