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公开(公告)号:US20150311089A1
公开(公告)日:2015-10-29
申请号:US14746655
申请日:2015-06-22
Applicant: Applied Materials, Inc.
Inventor: Sang Hyuk Kim , Dongqing Yang , Young S. Lee , Weon Young Jung , Sang-jin Kim , Ching-Mei Hsu , Anchuan Wang , Nitin K. Ingle
IPC: H01L21/311
CPC classification number: H01L21/3065 , C23C16/0245 , H01J37/32357 , H01J2237/334 , H01L21/02046 , H01L21/02068 , H01L21/31116 , H01L21/31122 , H01L21/32135 , H01L21/32136 , H01L21/76814
Abstract: Methods of selectively etching tungsten oxide relative to tungsten, silicon oxide, silicon nitride and/or titanium nitride are described. The methods include a remote plasma etch formed from a fluorine-containing precursor and/or hydrogen (H2). Plasma effluents from the remote plasma are flowed into a substrate processing region where the plasma effluents react with the tungsten oxide. The plasmas effluents react with exposed surfaces and selectively remove tungsten oxide while very slowly removing other exposed materials. In some embodiments, the tungsten oxide selectivity results partly from the presence of an ion suppression element positioned between the remote plasma and the substrate processing region. The ion suppression element reduces or substantially eliminates the number of ionically-charged species that reach the substrate.
Abstract translation: 描述了相对于钨,氧化硅,氮化硅和/或氮化钛选择性地蚀刻氧化钨的方法。 这些方法包括由含氟前体和/或氢(H 2)形成的远程等离子体蚀刻。 来自远程等离子体的等离子体流出物流入基板处理区域,其中等离子体流出物与氧化钨反应。 等离子体流出物与暴露的表面反应并选择性地去除氧化钨,同时非常缓慢地除去其它暴露的材料。 在一些实施方案中,氧化钨选择性部分地来自位于远程等离子体和基板处理区域之间的离子抑制元件的存在。 离子抑制元件减少或基本消除了到达衬底的离子充电物质的数量。
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公开(公告)号:US20240306391A1
公开(公告)日:2024-09-12
申请号:US18597057
申请日:2024-03-06
Applicant: Applied Materials, Inc.
Inventor: Hao-Ling Tang , Arvind Kumar , Mahendra Pakala , Keith Tatseun Wong , Yi-Hsuan Hsiao , Dongqing Yang , Mark Conrad , Rio Soedibyo , Minrui Yu
Abstract: Two-dimensional (2D) materials formed in very thin layers improve the operation of semiconductor devices. However, forming a contact on 2D material tends to damage and penetrate the 2D material. A relatively gentle etch process has been developed that is very selective to the 2D material and allows vertical holes to be etched down to the 2D material without damaging or penetrating the 2D material. A low-power deposition process forms a protective liner when performing the metal fill to further prevent damage to the 2D material when forming the metal contacts in the holes. These processes allow a vertical metal contact to be formed on a planar 2D material or a vertical sidewall contact be formed in a 3D NAND without damaging the 2D material. This increases the contact area, reduces the contact resistance, and improves the performance of the 2D material in the device.
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公开(公告)号:US11515179B2
公开(公告)日:2022-11-29
申请号:US16915749
申请日:2020-06-29
Applicant: Applied Materials, Inc.
Inventor: Mehmet Tugrul Samir , Dongqing Yang
IPC: H01L21/311 , H01L21/67 , C23C16/455 , H01J37/32 , C23C16/44 , B01F25/00 , B01F101/58
Abstract: Exemplary semiconductor processing systems may include a processing chamber, and may include a remote plasma unit coupled with the processing chamber. Exemplary systems may also include a mixing manifold coupled between the remote plasma unit and the processing chamber. The mixing manifold may be characterized by a first end and a second end opposite the first end, and may be coupled with the processing chamber at the second end. The mixing manifold may define a central channel through the mixing manifold, and may define a port along an exterior of the mixing manifold. The port may be fluidly coupled with a first trench defined within the first end of the mixing manifold. The first trench may be characterized by an inner radius at a first inner sidewall and an outer radius, and the first trench may provide fluid access to the central channel through the first inner sidewall.
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公开(公告)号:US20190252154A1
公开(公告)日:2019-08-15
申请号:US15942051
申请日:2018-03-30
Applicant: Applied Materials, Inc.
Inventor: Mehmet Tugrul Samir , Dongqing Yang , Dmitry Lubomirsky
IPC: H01J37/32 , H01L21/311 , H01L21/67
CPC classification number: H01J37/3244 , H01J2237/006 , H01J2237/334 , H01L21/31116 , H01L21/67069
Abstract: Exemplary semiconductor processing systems may include a processing chamber, and may include a remote plasma unit coupled with the processing chamber. Exemplary systems may also include a mixing manifold coupled between the remote plasma unit and the processing chamber. The mixing manifold may be characterized by a first end and a second end opposite the first end, and may be coupled with the processing chamber at the second end. The mixing manifold may define a central channel through the mixing manifold, and may define a port along an exterior of the mixing manifold. The port may be fluidly coupled with a first trench defined within the first end of the mixing manifold. The first trench may be characterized by an inner radius at a first inner sidewall and an outer radius, and the first trench may provide fluid access to the central channel through the first inner sidewall.
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公开(公告)号:US20180337057A1
公开(公告)日:2018-11-22
申请号:US15597973
申请日:2017-05-17
Applicant: Applied Materials, Inc.
Inventor: Mehmet Tugrul Samir , Dongqing Yang , Dmitry Lubomirsky , Peter Hillman , Soonam Park , Martin Yue Choy , Lala Zhu
IPC: H01L21/3065 , H01L21/67 , H01J37/32
Abstract: Exemplary semiconductor processing systems may include a processing chamber, and may include a remote plasma unit coupled with the processing chamber. Exemplary systems may also include an adapter coupled with the remote plasma unit. The adapter may include a first end and a second end opposite the first end. The adapter may define a central channel through the adapter. The adapter may define an exit from a second channel at the second end, and the adapter may define an exit from a third channel at the second end. The central channel, the second channel, and the third channel may each be fluidly isolated from one another within the adapter.
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36.
公开(公告)号:US20180337021A1
公开(公告)日:2018-11-22
申请号:US16000469
申请日:2018-06-05
Applicant: Applied Materials, Inc.
Inventor: Sang Won Kang , Nicholas Celeste , Dmitry Lubomirsky , Peter Hillman , Douglas Brenton Hayden , Dongqing Yang
IPC: H01J37/32
CPC classification number: H01J37/3244 , H01J37/32357 , H01J37/32449 , H01J37/32522 , H01J37/32724 , H01J37/32862
Abstract: Embodiments of the present disclosure generally provide improved methods for processing substrates with improved process stability, increased mean wafers between clean, and/or improved within wafer uniformity. One embodiment provides a method for seasoning one or more chamber components in a process chamber. The method includes placing a dummy substrate in the process chamber, flowing a processing gas mixture to the process chamber to react with the dummy substrate and generate a byproduct on the dummy substrate, and annealing the dummy substrate to sublimate the byproduct while at least one purge conduit of the process chamber is closed.
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公开(公告)号:US20170263438A1
公开(公告)日:2017-09-14
申请号:US15455766
申请日:2017-03-10
Applicant: Applied Materials, Inc.
Inventor: Ning Li , Mihaela Balseanu , Li-Qun Xia , Dongqing Yang , Anchuan Wang
IPC: H01L21/02 , H01L29/66 , H01L21/311
CPC classification number: H01L21/0217 , C23C16/345 , C23C16/45519 , C23C16/45551 , C23C16/45555 , C23C16/56 , H01L21/02211 , H01L21/02274 , H01L21/0228 , H01L21/0234 , H01L21/0337 , H01L21/3086 , H01L21/3105 , H01L21/31111 , H01L21/31116 , H01L29/6653
Abstract: Methods for forming a spacer comprising depositing a film on the top, bottom and sidewalls of a feature and treating the film to change a property of the film on the top and bottom of the feature. Selectively dry etching the film from the top and bottom of the feature relative to the film on the sidewalls of the feature using a high intensity plasma.
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公开(公告)号:US09659753B2
公开(公告)日:2017-05-23
申请号:US14454493
申请日:2014-08-07
Applicant: Applied Materials, Inc.
Inventor: Tae Cho , Sang Won Kang , Dongqing Yang , Raymond W. Lu , Peter Hillman , Nicholas Celeste , Tien Fak Tan , Soonam Park , Dmitry Lubomirsky
IPC: H01J37/32
CPC classification number: H01J37/3255 , H01J37/32082
Abstract: A plasma source includes a first electrode and a second electrode having respective surfaces, and an insulator that is between and in contact with the electrodes. The electrode surfaces and the insulator surface substantially define a plasma cavity. The insulator surface defines one or more grooves configured to prevent deposition of material in a contiguous form on the insulator surface. A method of generating a plasma includes introducing one or more gases into a plasma cavity defined by a first electrode, a surface of an insulator that is in contact with the first electrode, and a second electrode that faces the first electrode. The insulator surface defines one or more grooves where portions of the insulator surface are not exposed to a central region of the cavity. The method further includes providing RF energy across the first and second electrodes to generate the plasma within the cavity.
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公开(公告)号:US09064816B2
公开(公告)日:2015-06-23
申请号:US13839948
申请日:2013-03-15
Applicant: Applied Materials, Inc.
Inventor: Sang Hyuk Kim , Dongqing Yang , Young S. Lee , Weon Young Jung , Sang-jin Kim , Ching-Mei Hsu , Anchuan Wang , Nitin K. Ingle
IPC: B44C1/22 , H01L21/311 , H01L21/02 , H01J37/32
CPC classification number: H01L21/3065 , C23C16/0245 , H01J37/32357 , H01J2237/334 , H01L21/02046 , H01L21/02068 , H01L21/31116 , H01L21/31122 , H01L21/32135 , H01L21/32136 , H01L21/76814
Abstract: Methods of selectively etching tungsten oxide relative to tungsten, silicon oxide, silicon nitride and/or titanium nitride are described. The methods include a remote plasma etch formed from a fluorine-containing precursor and/or hydrogen (H2). Plasma effluents from the remote plasma are flowed into a substrate processing region where the plasma effluents react with the tungsten oxide. The plasmas effluents react with exposed surfaces and selectively remove tungsten oxide while very slowly removing other exposed materials. In some embodiments, the tungsten oxide selectivity results partly from the presence of an ion suppression element positioned between the remote plasma and the substrate processing region. The ion suppression element reduces or substantially eliminates the number of ionically-charged species that reach the substrate.
Abstract translation: 描述了相对于钨,氧化硅,氮化硅和/或氮化钛选择性地蚀刻氧化钨的方法。 这些方法包括由含氟前体和/或氢(H 2)形成的远程等离子体蚀刻。 来自远程等离子体的等离子体流出物流入基板处理区域,其中等离子体流出物与氧化钨反应。 等离子体流出物与暴露的表面反应并选择性地去除氧化钨,同时非常缓慢地除去其它暴露的材料。 在一些实施方案中,氧化钨选择性部分地来自位于远程等离子体和基板处理区域之间的离子抑制元件的存在。 离子抑制元件减少或基本消除了到达衬底的离子充电物质的数量。
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