公开(公告)号：US20050230716A1

公开(公告)日：2005-10-20

申请号：US11107888

申请日：2005-04-18

申请人： Satoshi Moriya ,  Toshiyuki Kikuchi ,  Akihiko Konno ,  Hidenori Sato ,  Naoki Yamamoto ,  Masamichi Matsuoka ,  Hiraku Chakihara ,  Akio Nishida

发明人： Satoshi Moriya ,  Toshiyuki Kikuchi ,  Akihiko Konno ,  Hidenori Sato ,  Naoki Yamamoto ,  Masamichi Matsuoka ,  Hiraku Chakihara ,  Akio Nishida

IPC分类号： H01L23/522 ,  H01L21/336 ,  H01L21/768 ,  H01L21/8234 ,  H01L21/8244 ,  H01L27/088 ,  H01L27/092 ,  H01L27/11 ,  H01L29/76

CPC分类号： H01L27/11 ,  H01L21/823425 ,  H01L21/823475 ,  H01L27/088 ,  H01L27/092 ,  H01L29/6656

摘要： The object of the present invention is to suppress the increase of the contact resistance at the interface between the metal layer and the silicon plug in the wiring structure in which a metal layer is formed on and connected to a silicon plug. For its achievement, a lower semiconductor layer (drain) of a vertical-type MISFET is connected to an intermediate metal layer via an underlying plug composed of a polycrystalline silicon film, and a trap layer composed of a silicon nitride (TiN) film is formed on a part of the surface of the intermediate metal layer so as to surround the plug. The trap layer is formed in order to prevent an undesired high-resistance oxide layer from being formed at the interface between the plug and the intermediate metal layer.

摘要翻译： 本发明的目的是为了抑制金属层与硅插头之间的界面处的接触电阻的增加，其中形成金属层并连接到硅插头的布线结构中。 为了实现，垂直型MISFET的下半导体层（漏极）经由由多晶硅膜构成的下面的插塞连接到中间金属层，并且形成由氮化硅（TiN）膜构成的捕获层 在中间金属层的表面的一部分上，以围绕塞子。 形成陷阱层以防止在插塞和中间金属层之间的界面处形成不期望的高电阻氧化物层。

公开(公告)号：US06943373B2

公开(公告)日：2005-09-13

申请号：US10693987

申请日：2003-10-28

申请人： Norikatsu Takaura ,  Hideyuki Matsuoka ,  Riichiro Takemura ,  Kousuke Okuyama ,  Masahiro Moniwa ,  Akio Nishida ,  Kota Funayama ,  Tomonori Sekiguchi

发明人： Norikatsu Takaura ,  Hideyuki Matsuoka ,  Riichiro Takemura ,  Kousuke Okuyama ,  Masahiro Moniwa ,  Akio Nishida ,  Kota Funayama ,  Tomonori Sekiguchi

IPC分类号： G11C11/41 ,  H01L21/8234 ,  H01L21/8244 ,  H01L27/00 ,  H01L27/06 ,  H01L27/088 ,  H01L27/10 ,  H01L27/11 ,  H01L29/10 ,  H01L29/72

CPC分类号： H01L27/11 ,  H01L27/0688 ,  H01L27/1104

摘要： The invention provides a semiconductor memory device comprising a plurality of word lines, a plurality of bit lines, and a plurality of static memory cells each having a first, second, third, fourth, fifth, and sixth transistors. While each of channels of the first, second, third, and fourth transistors are formed vertical against a substrate of the semiconductor memory device. Each of semiconductor regions forming a source or a drain of the fifth and sixth transistors forms a PN junction against the substrate. According to another aspect of the invention, the SRAM device of the invention has a plurality of SRAM cells, at least one of which is a vertical SRAM cell comprising at least four vertical transistors onto a substrate, and each vertical transistor includes a source, a drain, and a channel therebetween aligning in one aligning line which penetrates into the substrate surface at an angle greater than zero degree.

公开(公告)号：US06898090B2

公开(公告)日：2005-05-24

申请号：US10638395

申请日：2003-08-12

申请人： Akio Nishida ,  Hiroshi Takemura

发明人： Akio Nishida ,  Hiroshi Takemura

IPC分类号： H02M3/28 ,  H02M3/338 ,  H02M3/335

CPC分类号： H02M3/3381

摘要： A switching power supply unit includes a transformer including a primary winding, a secondary winding, and a feedback winding; an input power supply and a first switching element that are connected in series with the primary winding; a control circuit provided between one end of the feedback winding and a control terminal of the first switching element; a rectification circuit connected to the secondary winding; and an output voltage detection circuit for detecting output voltage output from the rectification circuit and for sending a feedback signal to the control circuit. The control circuit includes an on-period control circuit for stabilizing the output voltage by turning off the first switching element in an on-state in accordance with the feedback signal. The control circuit also includes an off-period control circuit for stabilizing the output voltage by delaying turning on of the first switching element in accordance with the feedback signal.

摘要翻译： 开关电源单元包括：变压器，包括初级绕组，次级绕组和反馈绕组; 与初级绕组串联连接的输入电源和第一开关元件; 设置在所述反馈绕组的一端和所述第一开关元件的控制端子之间的控制电路; 连接到次级绕组的整流电路; 以及输出电压检测电路，用于检测从整流电路输出的输出电压并将反馈信号发送到控制电路。 该控制电路包括一个接通周期控制电路，用于根据该反馈信号使接通状态下的第一开关元件断开来稳定输出电压。 控制电路还包括用于通过根据反馈信号延迟第一开关元件的导通来稳定输出电压的非周期控制电路。

公开(公告)号：US06611436B2

公开(公告)日：2003-08-26

申请号：US09984748

申请日：2001-10-31

申请人： Akio Nishida ,  Hiroshi Takemura

发明人： Akio Nishida ,  Hiroshi Takemura

IPC分类号： H02M3335

CPC分类号： H02M3/33561 ,  H02M3/3385

摘要： A switching power supply unit includes a control output circuit, a non-control output circuit, and a regulator circuit. With this switching power supply unit, it is no longer necessary to set the voltage of the non-control output to be greater than a required value when the control output circuit is unloaded or lightly loaded. The regulator circuit is connected to the non-control output circuit and includes a first transistor defining a first impedance element connected in series to the non-control output circuit, a second transistor defining a second impedance element connected between the control output circuit and the base of the first transistor, and a voltage control circuit controlling the impedance of the second transistor such that the output voltage of the regulator circuit is maintained constant.

摘要翻译： 开关电源单元包括控制输出电路，非控制输出电路和调节器电路。 利用该开关电源单元，当控制输出电路卸载或轻载时，不再需要将非控制输出的电压设置为大于所需值。 调节器电路连接到非控制输出电路，并且包括限定与非控制输出电路串联连接的第一阻抗元件的第一晶体管，限定连接在控制输出电路和基极之间的第二阻抗元件的第二晶体管 以及控制第二晶体管的阻抗的电压控制电路，使得调节器电路的输出电压保持恒定。

公开(公告)号：US06532159B2

公开(公告)日：2003-03-11

申请号：US09836767

申请日：2001-04-17

申请人： Akio Nishida ,  Hiroshi Takemura

发明人： Akio Nishida ,  Hiroshi Takemura

IPC分类号： H02M3335

CPC分类号： H02M3/3385 ,  H02M2001/0032 ,  Y02B70/16

摘要： A switching power supply unit comprises: a transformer, a main switching element, a rectifying smoothing circuit, a mode switching circuit and a delay circuit. The transformer has a primary winding, a secondary winding and a bias winding. The main switching element is connected to the primary winding and receives an output of the bias winding as a positive feedback so as to form a ringing choke converter operating in self-excitation oscillation. The rectifying smoothing circuit is connected to the bias winding. The mode switching circuit is turned on and off depending on whether or not the rectifying smoothing voltage of the rectifying smoothing circuit is a threshold voltage or higher. The delay circuit is coupled to the mode switching circuit and is connected between the main switching element and the bias winding and delays the output of the bias winding and applies the delayed output to the main switching element. The delay circuit lengthens a turn-on delay time when the mode switching circuit detects an output voltage of the rectifying smoothing circuit which is less than the threshold voltage.

公开(公告)号：US06498100B2

公开(公告)日：2002-12-24

申请号：US09996918

申请日：2001-11-30

申请人： Akio Nishida ,  Kikuo Kusukawa ,  Toshiaki Yamanaka ,  Natsuki Yokoyama ,  Shinichiro Kimura ,  Norio Suzuki ,  Osamu Tsuchiya ,  Atsushi Ogishima

发明人： Akio Nishida ,  Kikuo Kusukawa ,  Toshiaki Yamanaka ,  Natsuki Yokoyama ,  Shinichiro Kimura ,  Norio Suzuki ,  Osamu Tsuchiya ,  Atsushi Ogishima

IPC分类号： H01L21302

CPC分类号： H01L27/10894 ,  H01L21/31053 ,  H01L21/76229 ,  H01L21/823437 ,  H01L21/823481 ,  H01L27/10814

摘要： In a method of manufacturing a semiconductor device having a memory mat portion in which an active region and a field region are formed densely, after a polishing stopper film is deposited on a semiconductor substrate, there are formed grooves by etching a polishing stopper film of a field region and the semiconductor substrate. Then, after an insulating film is deposited so as to fill the grooves, then insulating film is partly removed from the memory mat portion by etching. Under this state, the insulating film is chemically mechanically polished until the polishing stopper film is exposed. The film thickness of the polishing stopper film on the active region can be reduced, and an electrical element isolation characteristic of the field region can be improved. At the same time, upon chemical mechanical polishing, a silicon substrate can be prevented from being exposed at the central portion of the memory mat portion and the insulating film can be prevented from being left on the silicon nitride film near the outer periphery, thereby making it possible to form elements having uniform electrical characteristics on all active regions of the memory mat portion.

公开(公告)号：US08476138B2

公开(公告)日：2013-07-02

申请号：US13150768

申请日：2011-06-01

申请人： Hiraku Chakihara ,  Kousuke Okuyama ,  Masahiro Moniwa ,  Makoto Mizuno ,  Keiji Okamoto ,  Mitsuhiro Noguchi ,  Tadanori Yoshida ,  Yasuhiko Takahshi ,  Akio Nishida

发明人： Hiraku Chakihara ,  Kousuke Okuyama ,  Masahiro Moniwa ,  Makoto Mizuno ,  Keiji Okamoto ,  Mitsuhiro Noguchi ,  Tadanori Yoshida ,  Yasuhiko Takahshi ,  Akio Nishida

IPC分类号： H01L21/336 ,  H01L21/8244 ,  H01L21/8239

CPC分类号： H01L29/6675 ,  H01L21/823885 ,  H01L27/105 ,  H01L27/11 ,  H01L27/1104 ,  H01L27/1116 ,  H01L29/7833 ,  H01L29/78642

摘要： Vertical MISFETs are formed over drive MISFETs and transfer MISFETs. The vertical MISFETs comprise rectangular pillar laminated bodies each formed by laminating a lower semiconductor layer (drain), an intermediate semiconductor layer, and an upper semiconductor layer (source), and gate electrodes formed on corresponding side walls of the laminated bodies with gate insulating films interposed therebetween. In each vertical MISFET, the lower semiconductor layer constitutes a drain, the intermediate semiconductor layer constitutes a substrate (channel region), and the upper semiconductor layer constitutes a source. The lower semiconductor layer, the intermediate semiconductor layer and the upper semiconductor layer are each comprised of a silicon film. The lower semiconductor layer and the upper semiconductor layer are doped with a p type and constituted of a p type silicon film.

公开(公告)号：US08437179B2

公开(公告)日：2013-05-07

申请号：US13528025

申请日：2012-06-20

申请人： Kenichi Osada ,  Koichiro Ishibashi ,  Yoshikazu Saitoh ,  Akio Nishida ,  Masaru Nakamichi ,  Naoki Kitai

发明人： Kenichi Osada ,  Koichiro Ishibashi ,  Yoshikazu Saitoh ,  Akio Nishida ,  Masaru Nakamichi ,  Naoki Kitai

IPC分类号： G11C11/40

CPC分类号： G11C11/412 ,  G11C11/40 ,  G11C11/413 ,  G11C11/418 ,  H01L21/823475 ,  H01L21/823493 ,  H01L21/823814 ,  H01L21/82385 ,  H01L27/088 ,  H01L27/092 ,  H01L27/105 ,  H01L27/1052 ,  H01L27/11 ,  H01L27/1104 ,  H01L27/1116 ,  H03K19/0016

摘要： The gate tunnel leakage current is increased in the up-to-date process, so that it is necessary to reduce the gate tunnel leakage current in the LSI which is driven by a battery for use in a cellular phone and which needs to be in a standby mode at a low leakage current. In a semiconductor integrated circuit device, the ground source electrode lines of logic and memory circuits are kept at a ground potential in an active mode, and are kept at a voltage higher than the ground potential in an unselected standby mode. The gate tunnel leakage current can be reduced without destroying data.

公开(公告)号：US20120238089A1

公开(公告)日：2012-09-20

申请号：US13488015

申请日：2012-06-04

申请人： Yasuaki YONEMOCHI ,  Hisakazu Otoi ,  Akio Nishida ,  Shigeru Shiratake

发明人： Yasuaki YONEMOCHI ,  Hisakazu Otoi ,  Akio Nishida ,  Shigeru Shiratake

IPC分类号： H01L21/283

CPC分类号： H01L27/11521 ,  H01L21/28273 ,  H01L21/7682 ,  H01L27/115 ,  H01L29/42324

摘要： A semiconductor substrate having a main surface, first and second floating gates formed spaced apart from each other on the main surface of the semiconductor substrate, first and second control gates respectively located on the first and second floating gates, a first insulation film formed on the first control gate, a second insulation film formed on the second control gate to contact the first insulation film, and a gap portion formed at least between the first floating gate and the second floating gate by achieving contact between the first insulation film and the second insulation film are included. With this, a function of a nonvolatile semiconductor device can be ensured and a variation in a threshold voltage of a floating gate can be suppressed.

摘要翻译： 一种具有主表面的半导体衬底，在半导体衬底的主表面上彼此隔开形成的第一和第二浮置栅极，分别位于第一和第二浮置栅极上的第一和第二控制栅极，形成在第一和第二浮置栅极上的第一绝缘膜 第一控制栅极，形成在第二控制栅极上以与第一绝缘膜接触的第二绝缘膜，以及通过实现第一绝缘膜和第二绝缘体之间的接触而形成在至少在第一浮栅和第二浮栅之间的间隙部分 包括电影。 由此，可以确保非易失性半导体器件的功能，并且可以抑制浮动栅极的阈值电压的变化。

公开(公告)号：US08211777B2

公开(公告)日：2012-07-03

申请号：US12727890

申请日：2010-03-19

申请人： Yasuaki Yonemochi ,  Hisakazu Otoi ,  Akio Nishida ,  Shigeru Shiratake

发明人： Yasuaki Yonemochi ,  Hisakazu Otoi ,  Akio Nishida ,  Shigeru Shiratake

IPC分类号： H01L21/76

CPC分类号： H01L27/11521 ,  H01L21/28273 ,  H01L21/7682 ,  H01L27/115 ,  H01L29/42324

摘要： A semiconductor substrate having a main surface, first and second floating gates formed spaced apart from each other on the main surface of the semiconductor substrate, first and second control gates respectively located on the first and second floating gates, a first insulation film formed on the first control gate, a second insulation film formed on the second control gate to contact the first insulation film, and a gap portion formed at least between the first floating gate and the second floating gate by achieving contact between the first insulation film and the second insulation film are included. With this, a function of a nonvolatile semiconductor device can be ensured and a variation in a threshold voltage of a floating gate can be suppressed.

摘要翻译： 一种具有主表面的半导体衬底，在半导体衬底的主表面上彼此隔开形成的第一和第二浮置栅极，分别位于第一和第二浮置栅极上的第一和第二控制栅极，形成在第一和第二浮置栅极上的第一绝缘膜 第一控制栅极，形成在第二控制栅极上以与第一绝缘膜接触的第二绝缘膜，以及通过实现第一绝缘膜和第二绝缘体之间的接触而形成在至少在第一浮栅和第二浮栅之间的间隙部分 包括电影。 由此，可以确保非易失性半导体器件的功能，并且可以抑制浮动栅极的阈值电压的变化。