公开(公告)号：US09978632B2

公开(公告)日：2018-05-22

申请号：US14730192

申请日：2015-06-03

Applicant: Applied Materials, Inc.

Inventor： Khiem Nguyen ,  Saravjeet Singh ,  Amitabh Sabharwal

IPC: H01L21/677 ,  H01L21/687 ,  H01L21/67 ,  C23C16/458 ,  H01J37/32

CPC classification number: H01L21/68742 ,  C23C16/458 ,  H01J37/32715 ,  H01J37/32788

Abstract: The present disclosure provides a substrate support assembly includes a substrate pedestal having an upper surface for receiving and supporting a substrate, a cover plate disposed on the substrate support pedestal, and two or more lift pins movably disposed through the substrate support pedestal and the cover plate. The cover plate includes a disk body having a central opening. The two or more lift pins are self supportive. Each of the two or more lift pins comprises one or more contact pads, and the contact pads of the lift pins extend into to the central opening of the cover plate to receive and support a substrate at an edge region of the substrate.

公开(公告)号：US09754765B2

公开(公告)日：2017-09-05

申请号：US14042490

申请日：2013-09-30

Applicant: Applied Materials, Inc.

Inventor： Banqiu Wu ,  Saravjeet Singh ,  Amitabh Sabharwal ,  Ajay Kumar

IPC: H01J37/32

CPC classification number: H01J37/32082 ,  H01J37/32541 ,  H01J37/32568 ,  H01J37/32577 ,  Y10T156/10

Abstract: An electrode having a first portion and a second portion is formed over a substrate to couple to a bias RF power. The first portion is configured to compensate for an electric field at the second portion to even out a distribution of an etching strength over a workpiece placed over the electrode.

公开(公告)号：US09224625B2

公开(公告)日：2015-12-29

申请号：US13943652

申请日：2013-07-16

Applicant: Applied Materials, Inc.

Inventor： Wei-Sheng Lei ,  Madhava Rao Yalamanchili ,  Brad Eaton ,  Saravjeet Singh ,  Ajay Kumar

IPC: H01L21/00 ,  H01L21/67 ,  H01L21/78 ,  H01L21/3065 ,  H01L21/308 ,  H01L21/683 ,  B23K26/06 ,  B23K26/36 ,  B23K26/40

CPC classification number: H01L21/67069 ,  B23K26/0624 ,  B23K26/364 ,  B23K26/40 ,  B23K2103/172 ,  B23K2103/50 ,  H01L21/3065 ,  H01L21/3081 ,  H01L21/67207 ,  H01L21/6836 ,  H01L21/78 ,  H01L2221/68327

Abstract: Methods of dicing semiconductor wafers, each wafer having a plurality of integrated circuits, are described. A method includes forming a mask above the semiconductor wafer. The semiconductor wafer is disposed on a water-soluble die attach film. The mask covers and protects the integrated circuits. The mask is patterned with a laser scribing process to provide a patterned mask with gaps. The patterning exposes regions of the semiconductor wafer between the integrated circuits. The semiconductor wafer is then etched through the gaps in the patterned mask to form singulated integrated circuits. The water-soluble die attach film is then patterned with an aqueous solution.

Abstract translation: 对具有多个集成电路的每个晶片进行切割的半导体晶片的方法进行了说明。 一种方法包括在半导体晶片上形成掩模。 半导体晶片设置在水溶性芯片附着膜上。 面罩覆盖并保护集成电路。 用激光划线工艺对掩模进行图案化以提供具有间隙的图案化掩模。 图案化使得集成电路之间的半导体晶片的区域露出。 然后通过图案化掩模中的间隙蚀刻半导体晶片，以形成单独的集成电路。 然后用水溶液对水溶性贴片膜进行构图。

公开(公告)号：US20140179108A1

公开(公告)日：2014-06-26

申请号：US13784591

申请日：2013-03-04

Applicant: Applied Materials, Inc.

Inventor： Dung Huu Le ,  Graeme Jamieson Scott ,  Jivko Dinev ,  Madhava Rao Yalamanchili ,  Khalid Mohiuddin Sirajuddin ,  Puneet Bajaj ,  Saravjeet Singh

IPC: H01L21/3065 ,  H01L21/67

CPC classification number: H01L21/3065 ,  H01J37/321 ,  H01J37/32623 ,  H01L21/67069

Abstract: Embodiments of the invention generally relate to an apparatus and method for plasma etching. In one embodiment, the apparatus includes a process ring with an annular step away from an inner wall of the ring and is disposed on a substrate support in a plasma process chamber. A gap is formed between the process ring and a substrate placed on the substrate support. The annular step has an inside surface having a height ranging from about 3 mm to about 6 mm. During operation, an edge-exclusion gas is introduced to flow through the gap and along the inside surface, so the plasma is blocked from entering the space near the edge of the substrate.

Abstract translation: 本发明的实施例一般涉及用于等离子体蚀刻的装置和方法。 在一个实施例中，该设备包括具有远离环的内壁的环形台阶并且设置在等离子体处理室中的基板支撑件上的处理环。 在工艺环和放置在衬底支架上的衬底之间形成间隙。 环形台阶具有高度范围为约3mm至约6mm的内表面。 在操作期间，引入边缘排除气体流过间隙并沿着内表面，从而阻止等离子体进入基板边缘附近的空间。

公开(公告)号：US20230207393A1

公开(公告)日：2023-06-29

申请号：US18116736

申请日：2023-03-02

Applicant: Applied Materials, Inc.

Inventor： Wei-Sheng Lei ,  Brad Eaton ,  Madhava Rao Yalamanchili ,  Saravjeet Singh ,  Ajay Kumar ,  James M. Holden

IPC: H01L21/822 ,  H01L21/308 ,  H01L21/67 ,  H01L21/78 ,  H01J37/32 ,  H01L23/544 ,  B23K26/36 ,  H01L21/3065

CPC classification number: H01L21/822 ,  B23K26/36 ,  H01J37/32889 ,  H01J37/32899 ,  H01L21/78 ,  H01L21/3065 ,  H01L21/3083 ,  H01L21/67069 ,  H01L21/67207 ,  H01L23/544 ,  H01L21/6836 ,  H01L21/67092 ,  H01L2924/0002

Abstract: Methods of dicing semiconductor wafers, each wafer having a plurality of integrated circuits, are described. A method includes forming a mask above the semiconductor wafer, the mask including a layer covering and protecting the integrated circuits. The mask and a portion of the semiconductor wafer are patterned with a laser scribing process to provide a patterned mask and to form trenches partially into but not through the semiconductor wafer between the integrated circuits. Each of the trenches has a width. The semiconductor wafer is plasma etched through the trenches to form corresponding trench extensions and to singulate the integrated circuits. Each of the corresponding trench extensions has the width.

公开(公告)号：US20230197416A1

公开(公告)日：2023-06-22

申请号：US18168467

申请日：2023-02-13

Applicant: Applied Materials, Inc.

Inventor： Saravjeet Singh ,  Kenneth D. Schatz ,  Alan Tso ,  Marlin Wijekoon ,  Dimitri Kioussis

IPC: H01J37/32 ,  H01L21/02

CPC classification number: H01J37/32449 ,  H01J37/32862 ,  H01L21/02049 ,  H01L21/31116

Abstract: The present technology includes improved gas distribution designs for forming uniform plasmas during semiconductor processing operations or for treating the interior of semiconductor processing chambers. While conventional gas distribution assemblies may receive a specific reactant or reactant ratio which is then distributed into the plasma region, the presently described technology allows for improved control of the reactant input distribution. The technology allows for separate flows of reactants to different regions of the plasma to offset any irregularities observed in process uniformity. A first precursor may be delivered to the center of the plasma above the center of the substrate/pedestal while a second precursor may be delivered to an outer portion of the plasma above an outer portion of the substrate/pedestal. In so doing, a substrate residing on the pedestal may experience a more uniform etch or deposition profile across the entire surface.

公开(公告)号：US20210189564A1

公开(公告)日：2021-06-24

申请号：US17176411

申请日：2021-02-16

Applicant: Applied Materials, Inc.

Inventor： Laksheswar Kalita ,  Soonam Park ,  Dmitry Lubomirsky ,  Tien Fak Tan ,  LokKee Loh ,  Saravjeet Singh ,  Tae Won Kim

IPC: C23C16/455 ,  C23C16/34 ,  H01L21/3213 ,  H01J37/32 ,  H01L21/285 ,  C23C16/458

Abstract: Exemplary semiconductor processing chamber showerheads may include a dielectric plate characterized by a first surface and a second surface opposite the first surface. The dielectric plate may define a plurality of apertures through the dielectric plate. The dielectric plate may define a first annular channel in the first surface of the dielectric plate, and the first annular channel may extend about the plurality of apertures. The dielectric plate may define a second annular channel in the first surface of the dielectric plate. The second annular channel may be formed radially outward from the first annular channel. The showerheads may also include a conductive material embedded within the dielectric plate and extending about the plurality of apertures without being exposed by the apertures. The conductive material may be exposed at the second annular channel.

公开(公告)号：US10699879B2

公开(公告)日：2020-06-30

申请号：US15955588

申请日：2018-04-17

Applicant: Applied Materials, Inc.

Inventor： Tien Fak Tan ,  Saravjeet Singh ,  Dmitry Lubomirsky ,  Tae Wan Kim ,  Kenneth D. Schatz ,  Tae Seung Cho ,  Lok Kee Loh

IPC: H01J37/32 ,  H01J37/04

Abstract: An apparatus for distributing plasma products includes first and second electrodes that each include planar surfaces. The first electrode forms first apertures from a first planar surface to a second planar surface; the second electrode forms second apertures from the third planar surface to the fourth planar surface. The electrodes couple through one or more adjustable couplers such that the third planar surface is disposed adjacent to the second planar surface with a gap therebetween, the gap having a gap distance. Each of the adjustable couplers has a range of adjustment. The first and second apertures are arranged such that for at least one position within the ranges of adjustment, none of the first apertures aligns with any of the second apertures to form an open straight-line path extending through both the first and second electrodes, and the gap distance is between 0.005 inch and 0.050 inch.

公开(公告)号：US20190189401A1

公开(公告)日：2019-06-20

申请号：US15847411

申请日：2017-12-19

Applicant: Applied Materials, Inc.

Inventor： Saravjeet Singh ,  Kenneth D. Schatz ,  Alan Tso ,  Marlin Wijekoon ,  Dimitri Kioussis

IPC: H01J37/32 ,  H01L21/02

CPC classification number: H01J37/32449 ,  H01J37/32862 ,  H01J2237/3323 ,  H01J2237/3344 ,  H01J2237/335 ,  H01L21/02049 ,  H01L21/02274 ,  H01L21/31116

Abstract: The present technology includes improved gas distribution designs for forming uniform plasmas during semiconductor processing operations or for treating the interior of semiconductor processing chambers. While conventional gas distribution assemblies may receive a specific reactant or reactant ratio which is then distributed into the plasma region, the presently described technology allows for improved control of the reactant input distribution. The technology allows for separate flows of reactants to different regions of the plasma to offset any irregularities observed in process uniformity. A first precursor may be delivered to the center of the plasma above the center of the substrate/pedestal while a second precursor may be delivered to an outer portion of the plasma above an outer portion of the substrate/pedestal. In so doing, a substrate residing on the pedestal may experience a more uniform etch or deposition profile across the entire surface.

公开(公告)号：US09245802B2

公开(公告)日：2016-01-26

申请号：US14476060

申请日：2014-09-03

Applicant: Applied Materials, Inc.

Inventor： Wei-Sheng Lei ,  Brad Eaton ,  Madhava Rao Yalamanchili ,  Saravjeet Singh ,  Ajay Kumar ,  James M. Holden

IPC: H01L21/00 ,  H01L21/78 ,  H01L21/308 ,  H01L21/822 ,  B23K26/36 ,  H01J37/32 ,  H01L23/544 ,  H01L21/67

CPC classification number: H01L21/822 ,  B23K26/36 ,  H01J37/32889 ,  H01J37/32899 ,  H01L21/3065 ,  H01L21/3083 ,  H01L21/67069 ,  H01L21/67092 ,  H01L21/67207 ,  H01L21/6836 ,  H01L21/78 ,  H01L23/544 ,  H01L2221/68327 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Methods of dicing semiconductor wafers, each wafer having a plurality of integrated circuits, are described. A method includes forming a mask above the semiconductor wafer, the mask including a layer covering and protecting the integrated circuits. The mask and a portion of the semiconductor wafer are patterned with a laser scribing process to provide a patterned mask and to form trenches partially into but not through the semiconductor wafer between the integrated circuits. Each of the trenches has a width. The semiconductor wafer is plasma etched through the trenches to form corresponding trench extensions and to singulate the integrated circuits. Each of the corresponding trench extensions has the width.

Abstract translation: 对具有多个集成电路的每个晶片进行切割的半导体晶片的方法进行了说明。 一种方法包括在半导体晶片上形成掩模，该掩模包括覆盖并保护集成电路的层。 通过激光划线工艺对掩模和半导体晶片的一部分进行构图，以提供图案化掩模，并在集成电路之间部分地形成沟槽而不通过半导体晶片。 每个沟槽都有一个宽度。 通过沟槽等离子体蚀刻半导体晶片以形成对应的沟槽延伸部分并对集成电路进行分割。 每个相应的沟槽延伸部具有宽度。