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    OPPORTUNISTIC MEASUREMENTS AND PROCESSING OF USER'S CONTEXT
    33.
    发明申请
    OPPORTUNISTIC MEASUREMENTS AND PROCESSING OF USER'S CONTEXT 审中-公开
    用户语境的机能测量与处理

    公开(公告)号：US20160157782A1

    公开(公告)日：2016-06-09

    申请号：US14563809

    申请日：2014-12-08

    Applicant: Arvind Kumar ,  Marisa Ahmad

    Inventor： Arvind Kumar ,  Marisa Ahmad

    IPC: A61B5/00 ,  A61B5/0452 ,  A61B5/0456 ,  G06N99/00 ,  A61B5/0205

    CPC classification number: A61B5/6897 ,  A61B5/02 ,  A61B5/02416 ,  A61B5/0456 ,  A61B5/6898 ,  A61B5/7246 ,  A61B5/7267 ,  A61B2560/0462 ,  A61B2562/0219

    Abstract: Embodiments of the present disclosure provide techniques and configurations for an apparatus for opportunistic measurements and processing of user's context. In one instance, the apparatus may include a sensor module with sensors disposed on a work surface to maintain direct or indirect contact with portions of user's limbs for a time period when the portions of user's limbs are disposed on the work surface, to obtain readings of first and second parameters of user's context over the time period of the direct or indirect contact; and a processing module to process the readings of the first and second parameters, including to identify a first feature of the first parameter and a second feature of the second parameter that is temporally correlated with the first feature, and determine a third parameter of the user's context based on the identified first and second features. Other embodiments may be described and/or claimed.

    Abstract translation: 本公开的实施例提供了用于机会主义测量和处理用户上下文的装置的技术和配置。 在一种情况下，该装置可以包括具有设置在工作表面上的传感器的传感器模块，以在用户肢体的部分设置在工作表面上的时间段内保持与使用者肢体的部分的直接或间接接触，以获得 在直接或间接联系的时间段内用户上下文的第一和第二参数; 以及处理模块，用于处理第一和第二参数的读数，包括识别与第一特征暂时相关的第一参数的第一特征和第二参数的第二特征，以及确定用户的第三参数 基于所识别的第一和第二特征的上下文。 可以描述和/或要求保护其他实施例。

    GEOFENCING
    35.
    发明申请
    GEOFENCING 有权
    地理学

    公开(公告)号：US20150223022A1

    公开(公告)日：2015-08-06

    申请号：US14126172

    申请日：2013-06-28

    Applicant: Arvind KUMAR ,  Adam ECKELS

    Inventor： Arvind Kumar ,  Adam Eckels

    IPC: H04W4/02

    CPC classification number: H04W4/021 ,  G08B21/22

    Abstract: In one embodiment an apparatus comprises logic, at least partially including hardware logic, configured to establish a geographic reference point, define one or more geofences relative to the geographic reference point determine, baaed on an input from at least one inertial sensor, a location of the apparatus relative to the geographic reference point, and generate a warning signal in response to a determination that the location of the apparatus is outside the one or snore geofences. Other embodiments may be described.

    Abstract translation: 在一个实施例中，一种装置包括至少部分地包括硬件逻辑的逻辑，其被配置为建立地理参考点，相对于地理参考点定义一个或多个地理位置确定来自至少一个惯性传感器的输入上的位置， 所述设备相对于所述地理参考点，并且响应于所述设备的位置在所述一个或打鼾地理围栏之外的确定而产生警告信号。 可以描述其他实施例。

    Methods and apparatuses for processing wake events of communication networks
    36.
    发明授权
    Methods and apparatuses for processing wake events of communication networks 有权
    处理通信网络唤醒事件的方法和装置

    公开(公告)号：US08839356B2

    公开(公告)日：2014-09-16

    申请号：US12006150

    申请日：2007-12-31

    Applicant: Michael A. Rothman ,  Arvind Kumar ,  Vincent J. Zimmer ,  Patrick G. Kutch ,  Omer Levy

    Inventor： Michael A. Rothman ,  Arvind Kumar ,  Vincent J. Zimmer ,  Patrick G. Kutch ,  Omer Levy

    IPC: G06F1/00 ,  G06F7/04 ,  G06F17/30 ,  H04L9/32 ,  H04L29/06 ,  G06F21/85

    CPC classification number: H04L63/08 ,  G06F1/3209 ,  G06F21/85 ,  H04L12/12 ,  H04L63/083 ,  Y02D50/40

    Abstract: Methods, apparatuses, and computer program products that respond to wake events of communication networks are disclosed. One or more embodiments comprise setting a wake password of a computing device, such as a notebook computer or a server. Some of the embodiments comprise receiving a wake request from a communications network, establishing a secure communication session, and setting the wake password with the secure communication session. Some embodiments comprise an apparatus having a network controller to allow a platform to communicate via a communications network, non-volatile memory that stores a wake password, and a management controller that may communicate with a management console via a secure communication session to update the wake password. One or more embodiments the network controller may wake management hardware and/or wake the management controller while keeping one or more of the devices in the power conservation mode.

    Abstract translation: 公开了响应通信网络的唤醒事件的方法，设备和计算机程序产品。 一个或多个实施例包括设置诸如笔记本计算机或服务器之类的计算设备的唤醒密码。 一些实施例包括从通信网络接收唤醒请求，建立安全通信会话，以及利用安全通信会话设置唤醒密码。 一些实施例包括具有网络控制器的设备，其允许平台经由通信网络进行通信，存储唤醒密码的非易失性存储器以及可以经由安全通信会话与管理控制台通信以更新唤醒的管理控制器 密码。 一个或多个实施例，网络控制器可以在保持一个或多个设备处于功率节省模式的同时唤醒管理硬件和/或唤醒管理控制器。

    Techniques for enabling multiple Vt devices using high-K metal gate stacks
    37.
    发明授权
    Techniques for enabling multiple Vt devices using high-K metal gate stacks 有权
    使用高K金属栅极堆叠实现多个Vt器件的技术

    公开(公告)号：US08680623B2

    公开(公告)日：2014-03-25

    申请号：US13433815

    申请日：2012-03-29

    Applicant: Martin M. Frank ,  Arvind Kumar ,  Vijay Narayanan ,  Vamsi K. Paruchuri ,  Jeffrey Sleight

    Inventor： Martin M. Frank ,  Arvind Kumar ,  Vijay Narayanan ,  Vamsi K. Paruchuri ,  Jeffrey Sleight

    IPC: H01L21/8244 ,  H01L21/70

    CPC classification number: H01L27/1104 ,  H01L27/11 ,  H01L27/1108

    Abstract: Techniques for combining transistors having different threshold voltage requirements from one another are provided. In one aspect, a semiconductor device comprises a substrate having a first and a second nFET region, and a first and a second pFET region; a logic nFET on the substrate over the first nFET region; a logic pFET on the substrate over the first pFET region; a SRAM nFET on the substrate over the second nFET region; and a SRAM pFET on the substrate over the second pFET region, each comprising a gate stack having a metal layer over a high-K layer. The logic nFET gate stack further comprises a capping layer separating the metal layer from the high-K layer, wherein the capping layer is further configured to shift a threshold voltage of the logic nFET relative to a threshold voltage of one or more of the logic pFET, SRAM nFET and SRAM pFET.

    Abstract translation: 提供了用于组合彼此具有不同阈值电压要求的晶体管的技术。 在一个方面，一种半导体器件包括具有第一和第二nFET区的衬底以及第一和第二pFET区; 在第一nFET区域上的衬底上的逻辑nFET; 在第一pFET区上的衬底上的逻辑pFET; 位于第二nFET区上的衬底上的SRAM nFET; 以及在第二pFET区上的衬底上的SRAM pFET，每个包括在高K层上具有金属层的栅极堆叠。 逻辑nFET栅极堆叠还包括将金属层与高K层分隔开的覆盖层，其中封盖层还被配置为相对于逻辑pFET中的一个或多个的阈值电压移动逻辑nFET的阈值电压 ，SRAM nFET和SRAM pFET。

    GATED DIODE STRUCTURE FOR ELIMINATING RIE DAMAGE FROM CAP REMOVAL
    40.
    发明申请
    GATED DIODE STRUCTURE FOR ELIMINATING RIE DAMAGE FROM CAP REMOVAL 失效
    用于消除从盖拆卸中的RIE损伤的栅极二极管结构

    公开(公告)号：US20130328124A1

    公开(公告)日：2013-12-12

    申请号：US13489537

    申请日：2012-06-06

    Applicant: Anthony I. Chou ,  Arvind Kumar ,  Edward P. Maciejewski ,  Shreesh Narasimha ,  Dustin K. Slisher

    Inventor： Anthony I. Chou ,  Arvind Kumar ,  Edward P. Maciejewski ,  Shreesh Narasimha ,  Dustin K. Slisher

    IPC: H01L27/06 ,  H01L21/8238

    CPC classification number: H01L21/8238 ,  H01L21/265 ,  H01L21/77 ,  H01L21/823835 ,  H01L27/0629 ,  H01L27/1203 ,  H01L29/42364 ,  H01L29/7391 ,  H01L29/861

    Abstract: A semiconductor structure provided with a plurality of gated-diodes having a silicided anode (p-doped region) and cathode (n-doped region) and a high-K gate stack made of non-silicided gate material, the gated-diodes being adjacent to FETs, each of which having a silicided source, a silicided drain and a silicided HiK gate stack. The semiconductor structure eliminates a cap removal RIE in a gate first High-K metal gate flow from the region of the gated-diode. The lack of silicide and the presence of a nitride barrier on the gate of the diode are preferably made during the gate first process flow. The absence of the cap removal RIE is beneficial in that diffusions of the diode are not subjected to the cap removal RIE, which avoids damage and allows retaining its highly ideal junction characteristics.

    Abstract translation: 一种半导体结构，其具有多个具有硅化阳极（p掺杂区域）和阴极（n掺杂区域）的门控二极管和由非硅化栅极材料制成的高K栅极堆叠，该门控二极管相邻 其中每一个具有硅化源，硅化物漏极和硅化HiK栅极叠层。 半导体结构消除了栅极第一高K金属栅极流从栅极二极管的区域流出的帽去除RIE。 优选在栅极第一工艺流程期间，在二极管的栅极上缺少硅化物和存在氮化物阻挡层。 没有帽去除RIE是有益的，因为二极管的扩散不经受帽去除RIE，这避免了损伤并且允许保持其高度理想的结特性。

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