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    EXECUTION CONTEXT SWAP BETWEEN HETEROGENOUS FUNCTIONAL HARDWARE UNITS
    32.
    发明申请
    EXECUTION CONTEXT SWAP BETWEEN HETEROGENOUS FUNCTIONAL HARDWARE UNITS 有权
    执行异构功能硬件单元之间的上下文交换

    公开(公告)号：US20140281380A1

    公开(公告)日：2014-09-18

    申请号：US13795338

    申请日：2013-03-12

    申请人： Inder M. Sodhi ,  Marc Torrant ,  Zeev Offen ,  Michael Mishaeli ,  Ashish V. Choubal ,  Jason W. Brandt

    发明人： Inder M. Sodhi ,  Marc Torrant ,  Zeev Offen ,  Michael Mishaeli ,  Ashish V. Choubal ,  Jason W. Brandt

    IPC分类号： G06F15/76

    CPC分类号： G06F9/30123 ,  G06F1/32 ,  G06F1/3243 ,  G06F1/3287 ,  G06F9/3836 ,  G06F9/461 ,  Y02D10/152 ,  Y02D10/171

    摘要： Remapping technologies for execution context swap between heterogeneous functional hardware units are described. A computing system includes multiple registers configured to store remote contexts of functional units. A mapping table maps the remote context to the functional units. An execution unit is configured to execute a remapping tool that intercepts an operation to access a remote context of a first functional unit of the plurality of functional units that is taken offline. The remapping tool determines that the first functional unit is remapped to a second functional unit using the mapping table. The operation is performed to access the remote context that is remapped to the second functional unit. The first functional unit and the second functional unit may be heterogeneous functional units.

    摘要翻译： 描述用于异构功能硬件单元之间执行上下文交换的重新映射技术。 计算系统包括配置成存储功能单元的远程上下文的多个寄存器。 映射表将远程上下文映射到功能单元。 执行单元被配置为执行重新映射工具，该重新映射工具拦截用于访问脱机的多个功能单元中的第一功能单元的远程上下文的操作。 重新映射工具确定使用映射表将第一功能单元重新映射到第二功能单元。 执行操作以访问被重新映射到第二功能单元的远程上下文。 第一功能单元和第二功能单元可以是异构功能单元。

    Method, apparatus, and system for energy efficiency and energy conservation including improved processor core deep power down exit latency by using register secondary uninterrupted power supply
    33.
    发明授权
    Method, apparatus, and system for energy efficiency and energy conservation including improved processor core deep power down exit latency by using register secondary uninterrupted power supply 有权
    节能和节能的方法，装置和系统，包括通过使用寄存器二次不间断电源提高处理器核心深度掉电退出延迟

    公开(公告)号：US08819461B2

    公开(公告)日：2014-08-26

    申请号：US13335880

    申请日：2011-12-22

    申请人： Inder M. Sodhi ,  Alon Naveh ,  Michael Zelikson ,  Sanjeev s. Jahagirdar ,  Varghese George

    发明人： Inder M. Sodhi ,  Alon Naveh ,  Michael Zelikson ,  Sanjeev s. Jahagirdar ,  Varghese George

    IPC分类号： G06F1/00

    CPC分类号： G06F1/3296 ,  G06F1/3287 ,  Y02D10/171 ,  Y02D10/172

    摘要： Embodiments of the invention relate to improving exit latency from computing device processor core deep power down. Processor state data may be maintained during deep power down mode by providing a secondary uninterrupted voltage supply to always on keeper circuits that reside within critical state registers of the processor. When these registers receive a control signal indicating that the processor power state is going to be reduced from an active processor power state to a zero processor power state, they write critical state data from the critical state register latches to the keeper circuits that are supplied with the uninterrupted power. Then, when a register receives a control signal indicating that a processor power state of the processor is going to be increased back to an active processor power state, the critical state data stored in the keeper circuits is written back to the critical state register latches.

    摘要翻译： 本发明的实施例涉及从计算设备处理器核心深度掉电来改善退出等待时间。 处理器状态数据可以在深度掉电模式期间通过提供第二不间断电压供应来始终保持驻留在处理器的关键状态寄存器内的保持器电路。 当这些寄存器接收到指示处理器电源状态将从活动处理器电源状态降低到零处理器电源状态的控制信号时，它们将临界状态数据从临界状态寄存器锁存器写入到所提供的保持器电路 不间断的电源。 然后，当寄存器接收到指示处理器的处理器电源状态将增加回到活动处理器功率状态的控制信号时，存储在保持器电路中的临界状态数据被写回到临界状态寄存器锁存器。

    Method, apparatus, and system for energy efficiency and energy conservation including dynamic cache sizing and cache operating voltage management for optimal power performance
    35.
    发明授权
    Method, apparatus, and system for energy efficiency and energy conservation including dynamic cache sizing and cache operating voltage management for optimal power performance 有权
    能量效率和节能的方法，装置和系统，包括动态高速缓存大小和高速缓存操作电压管理，实现最佳功率性能

    公开(公告)号：US08713256B2

    公开(公告)日：2014-04-29

    申请号：US13336977

    申请日：2011-12-23

    申请人： Inder M. Sodhi ,  Satish K. Damaraju ,  Sanjeev S. Jahagirdar ,  Ryan D. Wells

    发明人： Inder M. Sodhi ,  Satish K. Damaraju ,  Sanjeev S. Jahagirdar ,  Ryan D. Wells

    IPC分类号： G06F12/00

    CPC分类号： G06F12/0895 ,  G06F1/3225 ,  G06F1/3275 ,  G06F1/3296 ,  Y02D10/14 ,  Y02D10/172

    摘要： Embodiments described herein vary an amount of cache available for use by a processor, and an amount of power supplied to the cache and to the processor, based on the amount of cache actually being used by the processor to process data. For example, a power control unit (PCU) may monitor a last level cache (LLC) to identify if the size or amount of the cache being used by a processor to process data and to determine heuristics based on that amount. Based on the monitored amount of cache being used and the heuristics, the PCU causes a corresponding decrease or increase in an amount of the cache available for use by the processor, and a corresponding decrease or increase in an amount of power supplied to the cache and to the processor.

    摘要翻译： 本文描述的实施例基于处理器实际使用的缓存的量来改变可用于由处理器使用的高速缓存的数量和提供给高速缓存和处理器的功率量。 例如，功率控制单元（PCU）可以监视最后一级高速缓存（LLC）以识别处理器正在使用的高速缓存的大小或数量来处理数据，并且基于该量来确定启发式。 基于所使用的缓存的监视量和启发式，PCU引起可用于处理器的缓存的量的相应减少或增加，并且相应地降低或增加提供给高速缓存的功率量，以及 到处理器。

    DYNAMIC POWER LIMIT SHARING IN A PLATFORM
    36.
    发明申请
    DYNAMIC POWER LIMIT SHARING IN A PLATFORM 有权
    动态功率限制在平台中共享

    公开(公告)号：US20130332753A1

    公开(公告)日：2013-12-12

    申请号：US13976687

    申请日：2012-03-29

    申请人： Ankush Varma ,  Krishnakanth V. Sistla ,  Cesar A. Quiroz ,  Vivek Garg ,  Martin T. Rowland ,  Inder M. Sodhi ,  James S. Burns

    发明人： Ankush Varma ,  Krishnakanth V. Sistla ,  Cesar A. Quiroz ,  Vivek Garg ,  Martin T. Rowland ,  Inder M. Sodhi ,  James S. Burns

    IPC分类号： G06F1/26

    CPC分类号： G06F1/3287 ,  G06F1/26 ,  G06F1/324 ,  G06F1/3275 ,  G06F1/3296 ,  Y02D10/126 ,  Y02D10/14 ,  Y02D10/172

    摘要： A method and apparatus for dynamic power limit sharing among the modules in the platform. In one embodiment of the invention, the platform comprises a processor and memory modules. By expanding the power domain to include the processor and the memory modules, dynamic sharing of the power budget of the platform between the processor and the memory modules is enabled. For low-bandwidth workloads, the dynamic sharing of the power budget offers significant opportunity for the processor to increase its frequency by using the headroom in the memory power and vice versa. This enables higher peak performance for the same total platform power budget in one embodiment of the invention.

    摘要翻译： 一种用于在平台中的模块之间动态功率限制共享的方法和装置。 在本发明的一个实施例中，平台包括处理器和存储器模块。 通过扩展功率域以包括处理器和存储器模块，能够在处理器和存储器模块之间动态共享平台的功率预算。 对于低带宽工作负载，功率预算的动态共享为处理器通过使用存储器电源中的余量增加频率提供了重要机会，反之亦然。 这在本发明的一个实施例中能够实现相同的总平台功率预算的更高峰值性能。

    Synchronized media processing
    37.
    发明授权
    Synchronized media processing 有权
    同步媒体处理

    公开(公告)号：US08279213B2

    公开(公告)日：2012-10-02

    申请号：US12655124

    申请日：2009-12-23

    申请人： Nikos Kaburlasos ,  Inder M. Sodhi

    发明人： Nikos Kaburlasos ,  Inder M. Sodhi

    IPC分类号： G09G5/00 ,  G06F1/26 ,  G06F1/00

    CPC分类号： G06F1/329 ,  G06F1/3228 ,  G06T1/20 ,  Y02D10/24 ,  Y02D50/20

    摘要： An electronic device comprises a central processing unit, a graphics processing unit, and a power control unit comprising logic to develop a predictive model of power states for a central processing unit in the electronic device, and use the predictive model to synchronize activity of a graphics processing unit in the electronic device with periods of activity in the central processing unit. Other embodiments may be described.

    摘要翻译： 电子设备包括中央处理单元，图形处理单元和功率控制单元，其包括用于开发电子设备中的中央处理单元的功率状态的预测模型的逻辑，并且使用预测模型来同步图形的活动 处理单元，其具有在中央处理单元中的活动周期的电子设备。 可以描述其他实施例。