公开(公告)号：US06445073B1

公开(公告)日：2002-09-03

申请号：US09002326

申请日：1998-01-02

Applicant: Bin Zhao

Inventor： Bin Zhao

IPC: H01L2940

CPC classification number: H01L21/7681 ,  H01L21/76807 ,  H01L21/7684 ,  H01L2221/1036

Abstract: A semiconductor process and structure is provided for use in single or dual damascene metallization processes. A thin metal layer which serves as an etch stop and masking layer is deposited upon a first dielectric layer. Then, a second dielectric layer is deposited upon the thin metallization masking layer. The thin metallization masking layer provides an etch stop to form the bottom of the in-laid conductor grooves. In a dual damascene process, the thin metallization masking layer leaves open the via regions. Thus, the conductor grooves above the metallization masking layer and the via regions may be etched in the first and second dielectric in one step. In a single damascene process, the thin metallization etch masking layer may cover the via regions. The etch stop and masking layer can be formed from any conductive or non-conductive materials whose chemical, mechanical, thermal and electrical properties are compatible with the process and circuit performance.

Abstract translation: 提供半导体工艺和结构用于单镶嵌金属化或双镶嵌金属化工艺。 用作蚀刻停止和掩蔽层的薄金属层沉积在第一介电层上。 然后，在薄金属化掩模层上沉积第二介电层。 薄金属化掩模层提供蚀刻停止以形成嵌入式导体槽的底部。 在双镶嵌工艺中，薄的金属化掩模层离开通孔区域。 因此，金属化掩模层和通孔区域之上的导体沟槽可以在一个步骤中在第一和第二电介质中蚀刻。 在单个镶嵌工艺中，薄金属化蚀刻掩模层可以覆盖通孔区域。 蚀刻停止和掩蔽层可以由其化学，机械，热和电特性与工艺和电路性能兼容的任何导电或非导电材料形成。

公开(公告)号：US06309922B1

公开(公告)日：2001-10-30

申请号：US09627505

申请日：2000-07-28

Applicant: Q. Z. Liu ,  Bin Zhao ,  David Howard

Inventor： Q. Z. Liu ,  Bin Zhao ,  David Howard

IPC: H01L218234

CPC classification number: H01L28/10 ,  H01L27/08

Abstract: Method for fabrication of on-chip inductors and related structure are disclosed. According to one embodiment, inductors are formed by patterning conductors within a certain dielectric layer in a semiconductor die. Thereafter, the entire dielectric layer in the semiconductor die is subjected to a blanket implantation or sputtering of high permeability material. According to another embodiment, a first area in a semiconductor die is covered, for example, with photoresist. A second area in the semiconductor die includes a patterned conductor which is to be used as an inductor. The patterned conductor is also covered, for example, with photoresist. The second area, excluding the covered patterned conductor is subjected to implantation or sputtering of high permeability material. According to yet another embodiment, a first area of a semiconductor die is covered, for example, with photoresist. A second area in the semiconductor area includes a patterned conductor which is to be used as an inductor. This second area, including the patterned conductor, is subjected to implantation or sputtering of high permeability material. The implantation or sputtering of high permeability materials result in the inductors having much higher inductance values than they would otherwise have.

Abstract translation: 公开了片上电感器的制造方法和相关结构。 根据一个实施例，电感器通过在半导体管芯内的某个介电层内图案化导体而形成。 此后，对半导体管芯中的整个电介质层进行高导磁率材料的覆盖注入或溅射。 根据另一实施例，半导体管芯中的第一区域例如被光致抗蚀剂覆盖。 半导体管芯中的第二区域包括用作电感器的图案化导体。 图案化的导体也例如用光致抗蚀剂覆盖。 不包括覆盖图案导体的第二区域经受高磁导率材料的注入或溅射。 根据另一个实施例，半导体管芯的第一区域例如被光致抗蚀剂覆盖。 半导体区域中的第二区域包括用作电感器的图案化导体。 包括图案化导体的该第二区域经受高磁导率材料的注入或溅射。 高磁导率材料的注入或溅射导致电感器的电感值高于原来的电感值。

公开(公告)号：US06271127B1

公开(公告)日：2001-08-07

申请号：US09329569

申请日：1999-06-10

Applicant: Qizhi Liu ,  David Feiler ,  Bin Zhao ,  Maureen R. Brongo

Inventor： Qizhi Liu ,  David Feiler ,  Bin Zhao ,  Maureen R. Brongo

IPC: H01L214763

CPC classification number: H01L21/76829 ,  H01L21/7681 ,  H01L21/76811 ,  H01L21/76825 ,  Y10S438/949

Abstract: Method for dual damascene metallization of semiconductor workpieces which uses a process for creating an etch stop in an insulator thereby eliminating the need for deposition of an etch stop layer. Electron beam exposure is used to cure the insulator, or material having a low dielectric constant. Application of the electron beam to the low dielectric constant material converts the topmost layer of the low dielectric constant material to an etch stop layer, while rapid thermal heating cures the remainder of the low dielectric constant material. Creation of an etch stop layer in the low dielectric constant material can also be achieved by curing the low dielectric constant material using ion implantation.

Abstract translation: 用于半导体工件的双镶嵌金属化的方法，其使用在绝缘体中产生蚀刻停止的工艺，从而消除了沉积蚀刻停止层的需要。 使用电子束曝光来固化绝缘体或具有低介电常数的材料。 将电子束应用于低介电常数材料将低介电常数材料的最上层转化为蚀刻停止层，同时快速热加热固化低介电常数材料的其余部分。 在低介电常数材料中形成蚀刻停止层也可以通过使用离子注入固化低介电常数材料来实现。

公开(公告)号：US06245663B1

公开(公告)日：2001-06-12

申请号：US09163967

申请日：1998-09-30

Applicant: Bin Zhao ,  Maureen R. Brongo

Inventor： Bin Zhao ,  Maureen R. Brongo

IPC: H01L214763

CPC classification number: H01L21/76834 ,  H01L21/76807 ,  H01L23/5329 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Methods and structures are disclosed for advanced interconnects in sub-micron and sub-half-micron integrated circuit devices fabricated using a single damascene process. a dielectric etch-stop layer (e.g., silicon nitride) is deposited subsequent to rather than prior to CMP processing of the previous metallization layer (e.g., the conductive plug). This scheme effectively eliminates the effect of CMP-induced erosion on the etch-stop layer and therefore allows an extremely thin etch stop to be used. Moreover, a high etch-selectivity can be obtained for the trench etch, and all etch-stop material is removed from beneath the interconnect metal, thereby reducing parasitic effects. A patterned dielectric layer is used as a metal cap in place of the standard blanket silicon nitride layer, thus preventing the formation of blisters and bubbles associated with trapped moisture and gasses, and reducing interconnect capacitance.

Abstract translation: 公开了使用单个镶嵌工艺制造的亚微米级和次级半微米集成电路器件中的高级互连的方法和结构。 在先前的金属化层（例如，导电插头）的CMP处理之前而不是之前沉积介电蚀刻停止层（例如，氮化硅）。 该方案有效地消除了CMP腐蚀对蚀刻停止层的影响，因此允许使用极薄的蚀刻停止。 此外，可以获得沟槽蚀刻的高蚀刻选择性，并且从互连金属下方去除所有蚀刻停止材料，从而减少寄生效应。 图案化的介电层用作代替标准覆盖氮化硅层的金属盖，从而防止与被捕获的湿气和气体相关联的起泡和气泡的形成，并减少互连电容。

公开(公告)号：US6037664A

公开(公告)日：2000-03-14

申请号：US52215

申请日：1998-03-31

Applicant: Bin Zhao ,  Prahalad K. Vasudev ,  Ronald S. Horwath ,  Thomas E. Seidel ,  Peter M. Zeitzoff

Inventor： Bin Zhao ,  Prahalad K. Vasudev ,  Ronald S. Horwath ,  Thomas E. Seidel ,  Peter M. Zeitzoff

IPC: H01L21/768 ,  H01L23/522 ,  H01L23/532 ,  H01L23/48

CPC classification number: H01L21/76849 ,  H01L21/7681 ,  H01L21/76843 ,  H01L23/5226 ,  H01L23/53223 ,  H01L23/53238 ,  H01L23/5329 ,  H01L2924/0002 ,  Y10S438/902

Abstract: A technique for fabricating a dual damascene interconnect structure using a low dielectric constant material as a dielectric layer or layers. A low dielectric constant (low-.epsilon.) dielectric material is used to form an inter-level dielectric (ILD) layer between metallization layers and in which via and trench openings are formed in the low-.epsilon. ILD. The dual damascene technique allows for both the via and trench openings to be filled at the same time.

Abstract translation: 一种使用低介电常数材料作为电介质层或多层制造双镶嵌互连结构的技术。 使用低介电常数（低ε）电介质材料在金属化层之间形成层间介电层（ILD）层，其中在低εILD中形成通孔和沟槽开口。 双镶嵌技术允许通孔和沟槽开口同时被填充。

公开(公告)号：US5891513A

公开(公告)日：1999-04-06

申请号：US587262

申请日：1996-01-16

Applicant: Valery M. Dubin ,  Yosef Shacham-Diamand ,  Chiu H. Ting ,  Bin Zhao ,  Prahalad K. Vasudev

Inventor： Valery M. Dubin ,  Yosef Shacham-Diamand ,  Chiu H. Ting ,  Bin Zhao ,  Prahalad K. Vasudev

IPC: C23C18/16 ,  H01L21/288 ,  H01L21/768 ,  H01L23/532 ,  H05K3/04 ,  H05K3/38 ,  H05K3/42 ,  H05K3/46 ,  B05D5/12

CPC classification number: H01L21/76843 ,  C23C18/1603 ,  C23C18/1651 ,  C23C18/1689 ,  C23C18/1831 ,  C23C18/1879 ,  C23C18/54 ,  H01L21/288 ,  H01L21/76807 ,  H01L21/76874 ,  H01L21/76877 ,  H01L23/53238 ,  H05K3/388 ,  H05K3/465 ,  H01L2924/0002 ,  H05K2201/09563 ,  H05K2203/072 ,  H05K2203/0733 ,  H05K3/045 ,  H05K3/422 ,  H05K3/4661 ,  Y10S977/892

Abstract: A method of utilizing electroless copper deposition to form interconnects on a semiconductor wafer. Once a via or a trench is formed in a dielectric layer, a titanium nitride (TiN) or tantalum (Ta) barrier layer is blanket deposited. Then, a contact displacement technique is used to form a thin activation seed layer of copper on the barrier layer. An electroless deposition technique is then used to auto-catalytically deposit copper on the activated barrier layer. The electroless copper deposition continues until the via/trench is filled. Subsequently, the surface is polished by an application of chemical-mechanical polishing (CMP) to remove excess copper and barrier material from the surface, so that the only copper and barrier material remaining are in the via/trench openings. Then an overlying silicon nitride (SiN) layer is formed above the exposed copper in order to form a dielectric barrier layer. The copper interconnect is fully encapsulated from the adjacent material by the TiN (or Ta) and the SiN layers.

Abstract translation: 一种利用无电铜沉积在半导体晶片上形成互连的方法。 一旦在电介质层中形成通孔或沟槽，则氮化钛（TiN）或钽（Ta）阻挡层被覆盖沉积。 然后，使用接触位移技术在阻挡层上形成铜的薄的活化种子层。 然后使用无电沉积技术在活化的阻挡层上自动催化沉积铜。 继续进行化学镀铜沉积，直到通孔/沟槽被填充。 随后，通过施加化学机械抛光（CMP）来抛光表面以从表面去除多余的铜和阻挡材料，使得剩余的唯一的铜和阻挡材料在通孔/沟槽开口中。 然后，在暴露的铜上方形成覆盖氮化硅（SiN）层，以形成电介质阻挡层。 铜互连通过TiN（或Ta）和SiN层从相邻材料完全封装。

公开(公告)号：US5830805A

公开(公告)日：1998-11-03

申请号：US751631

申请日：1996-11-18

Applicant: Yosi Shacham-Diamand ,  Valery M. Dubin ,  Chiu H. Ting ,  Bin Zhao ,  Prahalad K. Vasudev

Inventor： Yosi Shacham-Diamand ,  Valery M. Dubin ,  Chiu H. Ting ,  Bin Zhao ,  Prahalad K. Vasudev

IPC: C23C18/16 ,  H01L21/288 ,  H01L21/44

CPC classification number: C23C18/1683 ,  H01L21/288 ,  C23C18/1619 ,  Y10S438/908 ,  Y10S438/913

Abstract: An electroless deposition apparatus and a method of electroless deposition that uses a single process chamber for performing multiple processes by moving through the process chamber a variety of fluids one at a time in a sequential order.

Abstract translation: 一种无电沉积装置和无电沉积方法，其使用单个处理室通过以顺序顺序一次一个地通过处理室移动各种流体来执行多个处理。

公开(公告)号：US10097925B2

公开(公告)日：2018-10-09

申请号：US15417208

申请日：2017-01-26

Applicant: Xun Di ,  Lipeng Ma ,  Ping Liang ,  Bin Zhao ,  Xudong Yan

Inventor： Xun Di ,  Lipeng Ma ,  Ping Liang ,  Bin Zhao ,  Xudong Yan

IPC: H04R7/12 ,  B32B3/28 ,  B32B5/12 ,  B32B37/06 ,  B32B37/10 ,  B32B38/18 ,  H04R31/00 ,  B29C70/00

Abstract: The present disclosure disclose a diaphragm dome, the diaphragm dome includes a first carbon fiber layer and a second carbon fiber layer which are alternatively arranged by stacking, the first carbon fiber layer and the second carbon fiber layer are respectively a single-layer structure formed by an one-way extended carbon fiber bundle, an extending direction of the carbon fiber bundle of the first carbon fiber layer is perpendicular to an extending direction of the carbon fiber bundle of the second carbon fiber layer, and a thickness difference exists between the first carbon fiber layer and the second carbon fiber layer. In the diaphragm dome provided by the present disclosure, the material has larger specific strength, thus can reduce the thickness of the diaphragm dome, the carbon fiber layers of the diaphragm dome are well adhered, which is not readily layered, and has good water resistance.

公开(公告)号：US20170048600A1

公开(公告)日：2017-02-16

申请号：US15082304

申请日：2016-03-28

Applicant: Xiaofeng Pu ,  Qun Xiang ,  Xudong Yan ,  Bin Zhao ,  Sheng Ye

Inventor： Xiaofeng Pu ,  Qun Xiang ,  Xudong Yan ,  Bin Zhao ,  Sheng Ye

IPC: H04R1/02 ,  H04R1/32

CPC classification number: H04R1/023 ,  H04R1/2811 ,  H04R31/00 ,  H04R2499/11

Abstract: A sound generating device is provided in the present disclosure. The sound generating device includes a shell providing a receiving cavity, a sound generating body received in the receiving cavity and assembled to the shell, sound absorbing material filled in the receiving cavity, and an isolating member attached on the sound generating body. The sound generating body includes at least one air hole, and the isolating member covers the at least one air hole, the isolating member is configured for isolating the sound absorbing material from entering the sound generating body. The present disclosure further provides a method for making a sound generating device.

Abstract translation: 本发明提供一种发声装置。 声音发生装置包括提供接收腔的外壳，容纳在接收腔中并组装到外壳上的声音发生体，填充在接收腔中的吸声材料以及附着在发声体上的隔离构件。 发声体包括至少一个气孔，隔离构件覆盖至少一个气孔，该隔离构件用于隔离吸音材料以进入发声体。 本公开还提供了一种用于制造声音产生装置的方法。

公开(公告)号：US08599915B2

公开(公告)日：2013-12-03

申请号：US13025201

申请日：2011-02-11

Applicant: Bin Zhao ,  Jack W. Cornish ,  Andrew M. Kameya ,  Weizhuang W. Xin

Inventor： Bin Zhao ,  Jack W. Cornish ,  Andrew M. Kameya ,  Weizhuang W. Xin

IPC: H03K7/08 ,  H03K9/08

CPC classification number: H05B33/0827 ,  G09G3/3406 ,  G09G2320/064

Abstract: First information is received at a first pulse width modulation (PWM) module responsive to a chip select signal being asserted at a chip select input of a communication bus of the first PWM module during a first time. The first information is latched at a control register of the first PWM module in response to a first logic transition of the chip select signal. A first PWM signal is provided at a first output of the first PWM module beginning a predetermined amount of time after the first logic transition of the chip select signal, the first PWM signal generated by the first PWM module based upon the first information.

Abstract translation: 响应于在第一时间期间在第一PWM模块的通信总线的芯片选择输入端被断言的芯片选择信号，第一脉冲宽度调制（PWM）模块接收第一信息。 响应于芯片选择信号的第一逻辑转换，第一信息被锁存在第一PWM模块的控制寄存器中。 第一PWM信号设置在第一PWM模块的第一输出处，在芯片选择信号的第一逻辑转换，基于第一信息由第一PWM模块产生的第一PWM信号之后开始预定的时间量。