公开(公告)号：US06972216B2

公开(公告)日：2005-12-06

申请号：US10768307

申请日：2004-01-29

申请人： Chien-Ping Huang ,  Chih-Ming Huang

发明人： Chien-Ping Huang ,  Chih-Ming Huang

IPC分类号： H01L23/31 ,  H01L23/433 ,  H01L23/495 ,  H01L23/50 ,  H01L21/50

CPC分类号： H01L23/552 ,  H01L23/3128 ,  H01L23/4334 ,  H01L23/49568 ,  H01L23/50 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L24/91 ,  H01L2224/05554 ,  H01L2224/48091 ,  H01L2224/48095 ,  H01L2224/4813 ,  H01L2224/48227 ,  H01L2224/48235 ,  H01L2224/49 ,  H01L2224/73221 ,  H01L2924/00014 ,  H01L2924/01029 ,  H01L2924/014 ,  H01L2924/10161 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/3025 ,  H01L2224/45099 ,  H01L2224/05599 ,  H01L2924/00012

摘要： A BGA (ball grid array) package with enhanced electrical and thermal performance, and a method for fabricating the BGA package, are proposed. This BGA package is characterized by the use of a power-connecting heat spreader and a ground-connecting heat spreader, which are respectively used to electrically connect power pad and ground pad to a packaged chip as well as to dissipate heat generated by the chip during operation. The ground-connecting heat spreader is arranged to entirely cover the chip, and thereby provides good shielding effect for the chip, which helps improve electrical performance of the chip during operation. Further, the ground-connecting heat spreader is partly exposed to outside of an encapsulation body that encapsulates the chip, by which satisfactory heat-dissipation efficiency can be achieved.

摘要翻译： 提出了具有增强的电气和热性能的BGA（球栅阵列）封装以及制造BGA封装的方法。 该BGA封装的特征在于使用功率连接散热器和接地连接散热器，其分别用于将电源焊盘和接地焊盘电连接到封装芯片，以及散发由芯片产生的热量 操作。 地面连接散热器布置成完全覆盖芯片，从而为芯片提供良好的屏蔽效果，有助于提高芯片在运行过程中的电气性能。 此外，地连接散热器部分地暴露于封装芯片的封装体的外部，由此可以实现令人满意的散热效率。

公开(公告)号：US06963135B2

公开(公告)日：2005-11-08

申请号：US10816339

申请日：2004-03-31

申请人： Cheng-Chian Chiang ,  Chih-Ming Huang ,  Chin-Huang Chang ,  Cheng-Hsu Hsiao ,  Min-Nan Tsai

发明人： Cheng-Chian Chiang ,  Chih-Ming Huang ,  Chin-Huang Chang ,  Cheng-Hsu Hsiao ,  Min-Nan Tsai

IPC分类号： G11C5/04 ,  H01L23/31 ,  H01L23/538 ,  H01L25/065 ,  H01L25/10 ,  H01L23/34

CPC分类号： H01L23/3121 ,  G11C5/04 ,  H01L23/5388 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/97 ,  H01L25/0652 ,  H01L25/0655 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/49171 ,  H01L2924/00014 ,  H01L2924/01079 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/00015 ,  H01L2224/05599 ,  H01L2924/00012

摘要： A semiconductor package includes two substrates each having a plurality of electrical connection pads, at least one chip mounted on each of the substrates, an encapsulation body formed on each of the substrates for encapsulating the chip, and an cover for receiving the substrates and the chips therein. The chip is electrically connected to the electrical connection pads. The electrical connection pads are exposed from the cover and located on the same surface or oppositely arranged. The substrates and the cover each substantially has a rectangular shape, with a longer side of each of the substrates being vertical to a longer side of the cover. The semiconductor package is incorporated with multiple chips to enhance the performance and memory capacity thereof, and the substrates are smaller than those in the prior art and thus are more cost-effective to fabricate.

摘要翻译： 半导体封装包括两个基板，每个基板具有多个电连接焊盘，安装在每个基板上的至少一个芯片，形成在每个基板上的封装体，用于封装芯片;以及盖，用于接收基板和芯片 其中。 芯片电连接到电连接焊盘。 电连接垫从盖子露出并位于相同的表面上或相对布置。 基板和盖子基本上具有矩形形状，每个基板的较长边与盖的较长边垂直。 半导体封装结合有多个芯片以提高其性能和存储器容量，并且衬底小于现有技术中的衬底，因此制造更具成本效益。

公开(公告)号：US20050202590A1

公开(公告)日：2005-09-15

申请号：US10846460

申请日：2004-05-14

申请人： Chien-Ping Huang ,  Cheng-Hsu Hsiao ,  Chih-Ming Huang

发明人： Chien-Ping Huang ,  Cheng-Hsu Hsiao ,  Chih-Ming Huang

IPC分类号： H01L21/44

CPC分类号： H01L21/6835 ,  H01L21/568 ,  H01L24/19 ,  H01L24/96 ,  H01L24/97 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/19 ,  H01L2224/20 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/73267 ,  H01L2224/97 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/12042 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/18162 ,  H01L2924/351 ,  H01L2924/3511 ,  H01L2224/82 ,  H01L2924/00

摘要： A wafer level semiconductor package with a build-up layer is provided, which includes a glass frame having a through hole for receiving a semiconductor chip therein, a low-modulus buffer material filled within the space formed between the semiconductor chip and the glass frame, a build-up layer formed on the glass frame and the semiconductor chip such that the build-up layer is electrically connected to the semiconductor chip, and a plurality of conductive elements mounted on the build-up layer so that the semiconductor chip is electrically connected to external devices. With the use of the glass frame and low-modulus buffer material, the wafer level semiconductor package thus-obtained is free from warpage, chip-crack, and delamination problems and the reliability thereof is enhanced. A method for fabricating the wafer level semiconductor package is also provided.

摘要翻译： 提供具有积层的晶片级半导体封装，其包括具有用于接收其中的半导体芯片的通孔的玻璃框架，填充在形成在半导体芯片和玻璃框架之间的空间内的低模量缓冲材料， 形成在所述玻璃框架和所述半导体芯片上的堆积层，使得所述积层层电连接到所述半导体芯片，以及安装在所述积层层上的多个导电元件，使得所述半导体芯片电连接 到外部设备。 通过使用玻璃框架和低模量缓冲材料，由此获得的晶片级半导体封装没有翘曲，芯片裂纹和分层问题，并且其可靠性得到提高。 还提供了一种用于制造晶片级半导体封装的方法。

公开(公告)号：US20050189659A1

公开(公告)日：2005-09-01

申请号：US11112145

申请日：2005-04-21

申请人： Chien Huang ,  Yu-Po Wang ,  Chih-Ming Huang

发明人： Chien Huang ,  Yu-Po Wang ,  Chih-Ming Huang

IPC分类号： H01L21/48 ,  H01L21/56 ,  H01L21/68 ,  H01L23/31 ,  H01L23/58

CPC分类号： H01L21/4857 ,  H01L21/4832 ,  H01L21/561 ,  H01L21/568 ,  H01L23/3121 ,  H01L23/58 ,  H01L24/48 ,  H01L24/49 ,  H01L24/97 ,  H01L2221/68345 ,  H01L2224/05554 ,  H01L2224/16 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/49171 ,  H01L2224/97 ,  H01L2924/00014 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/15183 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/18161 ,  H05K3/007 ,  H05K3/3457 ,  H05K3/4682 ,  H05K2203/0152 ,  H01L2224/85 ,  H01L2224/81 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

摘要： A semiconductor package and a fabrication method thereof are provided in which a dielectric material layer formed with a plurality of openings is used and a solder material is applied into each of the openings. A first copper layer and a second copper layer are in turn deposited over the dielectric material layer and solder materials, and the first and second copper layers are patterned to form a plurality of conductive traces each of which has a terminal coated with a metal layer. A chip is mounted on the conductive traces and electrically connected to the terminals by bonding wires, with the dielectric material layer and solder materials being exposed to the outside. This package structure can flexibly arrange the conductive traces and effectively shorten the bonding wires, thereby improve trace routability and quality of electrical connection for the semiconductor package.

公开(公告)号：USD493799S1

公开(公告)日：2004-08-03

申请号：US29195995

申请日：2003-12-18

申请人： Cheng-Chia Chiang ,  Chih-Ming Huang ,  Chin-Huang Chang ,  Cheng-Hsu Hsiao ,  Min-Nan Tsai

设计人： Cheng-Chia Chiang ,  Chih-Ming Huang ,  Chin-Huang Chang ,  Cheng-Hsu Hsiao ,  Min-Nan Tsai

公开(公告)号：US06703698B2

公开(公告)日：2004-03-09

申请号：US10157069

申请日：2002-05-29

申请人： Chien-Ping Huang ,  Chih-Ming Huang

发明人： Chien-Ping Huang ,  Chih-Ming Huang

IPC分类号： H01L2322

CPC分类号： H01L23/552 ,  H01L23/3128 ,  H01L23/4334 ,  H01L23/49568 ,  H01L23/50 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L24/91 ,  H01L2224/05554 ,  H01L2224/48091 ,  H01L2224/48095 ,  H01L2224/4813 ,  H01L2224/48227 ,  H01L2224/48235 ,  H01L2224/49 ,  H01L2224/73221 ,  H01L2924/00014 ,  H01L2924/01029 ,  H01L2924/014 ,  H01L2924/10161 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/3025 ,  H01L2224/45099 ,  H01L2224/05599 ,  H01L2924/00012

摘要： A BGA (ball grid array) package with enhanced electrical and thermal performance, and a method for fabricating the BGA package, are proposed. This BGA package is characterized by the use of a power-connecting heat spreader and a ground-connecting heat spreader, which are respectively used to electrically connect power pad and ground pad to a packaged chip as well as to dissipate heat generated by the chip during operation. The ground-connecting heat spreader is arranged to entirely cover the chip, and thereby provides good shielding effect for the chip, which helps improve electrical performance of the chip during operation. Further, the ground-connecting heat spreader is partly exposed to outside of an encapsulation body that encapsulates the chip, by which satisfactory heat-dissipation efficiency can be achieved.

公开(公告)号：US06380587B1

公开(公告)日：2002-04-30

申请号：US09706527

申请日：2000-11-03

申请人： Shing-Ren Sheu ,  Chung-Hsien Wu ,  Chih-Ming Huang

发明人： Shing-Ren Sheu ,  Chung-Hsien Wu ,  Chih-Ming Huang

IPC分类号： H01L2976

CPC分类号： H01L27/1126 ,  H01L27/105 ,  H01L27/11293

摘要： A semiconductor read-only memory (ROM) and a method of fabricating the same are provided. The ROM device is structured in such a manner that allows the fabrication to include a fewer number of mask processes. This makes it more cost effective and allows a cycle time that is shorter than that of the prior art. Moreover, the particular structure of the ROM device makes punchthrough less likely to occur between any neighboring pairs of the buried bit lines when the ROM device is further scaled down. The ROM device is constructed on a semiconductor substrate which is partitioned into a peripheral region and a cell region. A plurality of STI structures are formed at predefined locations in both the peripheral region and the cell region. Immediately after this, a first ion-implantation process can be performed on the cell region to form a plurality of buried bit lines. Subsequently, the dielectric isolation layers in all of the STI structures in the cell region are removed, leaving a plurality of empty trenches behind. A conformal insulating layer and a conductive layer are then successively formed over the wafer, and the conductive layer is further selectively removed to form a word line in the cell region and a gate in the peripheral region. In the code implantation process, selected channel regions between the buried bit lines are doped with impurities for code implantation of data into the ROM device.

公开(公告)号：US08241059B2

公开(公告)日：2012-08-14

申请号：US12792910

申请日：2010-06-03

申请人： Wei-Chao Huang ,  Chih-Ming Huang

发明人： Wei-Chao Huang ,  Chih-Ming Huang

IPC分类号： H01R13/621

CPC分类号： H01R12/7047

摘要： A connector and printed circuit board assembly includes a printed circuit board, a connector fixed on the printed circuit board, and a fixing board fixed on the connector, the fixing board defining a through hole, a connecting member fixed on the printed circuit board adjacent to the connector, a threaded retainer, and a threaded post securely connected with the connecting member. The threaded post passes through the through hole and seats the threaded retainer to lock the connector onto the printed circuit board.

摘要翻译： 连接器和印刷电路板组件包括印刷电路板，固定在印刷电路板上的连接器和固定在连接器上的固定板，固定板限定通孔，固定在印刷电路板上的连接件 连接器，螺纹保持器和与连接构件牢固连接的螺纹柱。 螺纹柱穿过通孔并安装螺纹固定器以将连接器锁定到印刷电路板上。

公开(公告)号：US07667421B2

公开(公告)日：2010-02-23

申请号：US11861838

申请日：2007-09-26

申请人： Chih-Ming Huang

发明人： Chih-Ming Huang

IPC分类号： H02P7/00

CPC分类号： H02P6/08 ,  H02P6/14

摘要： A torque compensation method and system for a DC brushless motor. When the DC brushless motor coupled with an asymmetric load is rotating, the difference between an instant current and an average current of a shunt resister is an index of adjusting control signals within an absolute rotor position for the purpose of approaching the corresponding instant current to the average current.

摘要翻译： 一种用于直流无刷电机的转矩补偿方法和系统。 当与非对称负载耦合的DC无刷电动机旋转时，分流电阻器的瞬时电流和平均电流之间的差异是在绝对转子位置内调整控制信号的指标，以便接近对应于瞬时电流 平均电流。

公开(公告)号：US20090294959A1

公开(公告)日：2009-12-03

申请号：US12315787

申请日：2008-12-04

申请人： Cheng-Chia Chiang ,  Chin-Huang Chang ,  Chien-Ping Huang ,  Chih-Ming Huang ,  Jung-Pin Huang

发明人： Cheng-Chia Chiang ,  Chin-Huang Chang ,  Chien-Ping Huang ,  Chih-Ming Huang ,  Jung-Pin Huang

IPC分类号： H01L23/522 ,  H01L23/532 ,  H01L23/28 ,  H01L23/31

CPC分类号： H01L23/4334 ,  H01L21/486 ,  H01L23/31 ,  H01L23/3128 ,  H01L23/3135 ,  H01L23/49827 ,  H01L24/97 ,  H01L2224/16225 ,  H01L2224/16235 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/97 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01087 ,  H01L2924/15311 ,  H01L2924/157 ,  H01L2924/3511 ,  H01L2924/00 ,  H01L2224/81

摘要： A semiconductor package device, a semiconductor package structure, and fabrication methods thereof are provided, which mainly includes disposing a plurality of semiconductor chips on a wafer formed with TSVs (Through Silicon Vias) and electrically connecting the semiconductor chips to the TSVs; encapsulating the semiconductor chips with an encapsulant; and disposing a hard component on the encapsulant. The hard component ensures flatness of the wafer during a solder bump process and provides support to the wafer during a singulation process such that the wafer can firmly lie on a singulation carrier, thereby overcoming the drawbacks of the prior art, namely difficulty in mounting of solder bumps, and difficulty in cutting of the wafer.

摘要翻译： 提供了一种半导体封装器件，半导体封装结构及其制造方法，其主要包括在形成有TSV（透硅通孔）的晶片上设置多个半导体芯片，并将半导体芯片与TSV电连接; 用密封剂封装半导体芯片; 并将硬组分设置在密封剂上。 硬组件确保了在焊料凸块工艺期间晶片的平整度，并且在单独化处理期间提供对晶片的支撑，使得晶片可以牢固地位于单个载体上，从而克服现有技术的缺点，即难以安装焊料 碰撞，切割晶片难度大。