公开(公告)号：US20060099745A1

公开(公告)日：2006-05-11

申请号：US10981925

申请日：2004-11-05

申请人： Ju-Wang Hsu ,  Ming-Huan Tsai ,  Chien-Hao Chen ,  Yi-Chun Huang

发明人： Ju-Wang Hsu ,  Ming-Huan Tsai ,  Chien-Hao Chen ,  Yi-Chun Huang

IPC分类号： H01L21/84 ,  H01L21/00

CPC分类号： H01L29/7842 ,  H01L21/823807 ,  H01L21/823835 ,  H01L21/823864 ,  H01L21/823878 ,  H01L29/7843 ,  Y10S438/938

摘要： An integrated advanced method for forming a semiconductor device utilizes a sacrificial stress layer as part of a film stack that enables spatially selective silicide formation in the device. The low-resistance portion of the device to be silicided includes NMOS transistors and PMOS transistors. The stressed film may be a tensile or compressive nitride film. An annealing process is carried out prior to the silicide formation process. During the annealing process, the stressed nitride film preferentially remains over either the NMOS transistors or PMOS transistors, but not both, to optimize device performance. A tensile nitride film remains over the NMOS transistors but not the PMOS transistors while a compressive nitride film remains over the PMOS transistors but not the NMOS transistors, during anneal.

摘要翻译： 用于形成半导体器件的集成先进方法利用牺牲应力层作为薄膜堆叠的一部分，其能够在器件中形成空间选择性硅化物。 要被硅化的器件的低电阻部分包括NMOS晶体管和PMOS晶体管。 应力膜可以是拉伸或压缩氮化物膜。 在硅化物形成工艺之前进行退火处理。 在退火过程中，应力氮化物膜优先保留在NMOS晶体管或PMOS晶体管之上，但不能同时保持在两者上，以优化器件性能。 在退火期间，拉伸氮化物膜保留在NMOS晶体管上，而不是PMOS晶体管，而压电氮化物膜保留在PMOS晶体管上，而不保留在NMOS晶体管上。

公开(公告)号：US20060086690A1

公开(公告)日：2006-04-27

申请号：US10971265

申请日：2004-10-21

申请人： Ming-Huan Tsai ,  Fong-Yuh Yen ,  Hun-Jan Tao

发明人： Ming-Huan Tsai ,  Fong-Yuh Yen ,  Hun-Jan Tao

IPC分类号： C23F1/00 ,  C03C25/68 ,  B44C1/22

CPC分类号： H01L21/31116

摘要： A method of dry etching a dielectric layer is provided that prevents or significantly reduces deep ultraviolet photoresist damage and bird's beak problems. The dry etch method provided comprises the steps of providing a substrate having a dielectric layer overlying at least a portion of the substrate's surface; applying a deep ultraviolet (DUV) photoresist mask having a pattern of exposed area on at least a portion of the dielectric layer; and etching the masked dielectric layer with a plasma formed from a mixture of gases comprising a gaseous fluorine species, hydrogen, and helium.

摘要翻译： 提供了干蚀刻电介质层的方法，其防止或显着降低深紫外光致抗蚀剂损伤和鸟嘴问题。 所提供的干蚀刻方法包括以下步骤：提供具有覆盖在基底表面的至少一部分上的介电层的基底; 在所述电介质层的至少一部分上施加具有暴露区域图案的深紫外（DUV）光致抗蚀剂掩模; 并用由包含气态氟物质，氢气和氦气的气体混合物形成的等离子体蚀刻掩蔽的电介质层。

公开(公告)号：US06838381B2

公开(公告)日：2005-01-04

申请号：US10329598

申请日：2002-12-26

申请人： Peng-Fu Hsu ,  Ming-Huan Tsai ,  Baw-Ching Perng ,  Ju-Wang Hsu ,  Yaun-Hung Chiu

发明人： Peng-Fu Hsu ,  Ming-Huan Tsai ,  Baw-Ching Perng ,  Ju-Wang Hsu ,  Yaun-Hung Chiu

IPC分类号： H01L21/285 ,  H01L21/768 ,  H01L21/44

CPC分类号： H01L21/28518 ,  H01L21/76802 ,  H01L21/76814 ,  H01L21/76829

摘要： A method of manufacturing a semiconductor device is provided. A nickel silicide layer (e.g., NiSi) is formed on a substrate. Next, a hydrogen plasma treatment may be performed on the silicide layer, which may induce the formation of metal/silicon hydride bonds in the silicide layer. An etch stop layer is formed over the silicide layer. A dielectric layer is formed over the etch stop layer. An opening is formed in the dielectric layer. A portion of the etch stop layer is etched away at the opening to expose at least a portion of the silicide layer therebeneath. The etch chemistry mixture used during the etching step preferably includes hydrogen gas. The change in sheet resistance for the exposed silicide layer portion at the opening after the etching step, as compared to before the etching step, is preferably not greater than about 0.10 ohms/square.

摘要翻译： 提供一种制造半导体器件的方法。 在衬底上形成硅化镍层（例如NiSi）。 接下来，可以在硅化物层上进行氢等离子体处理，这可能在硅化物层中引起金属/硅氢化物键的形成。 在硅化物层之上形成蚀刻停止层。 在蚀刻停止层上方形成介电层。 在电介质层中形成开口。 蚀刻停止层的一部分在开口处被蚀刻掉以暴露其下面的硅化物层的至少一部分。 在蚀刻步骤期间使用的蚀刻化学混合物优选包括氢气。 与蚀刻步骤之前相比，在蚀刻步骤之后的开口处的暴露的硅化物层部分的薄层电阻的变化优选不大于约0.10欧姆/平方。

公开(公告)号：US06780782B1

公开(公告)日：2004-08-24

申请号：US10357579

申请日：2003-02-04

申请人： Ming-Huan Tsai ,  Hun-Jan Tao ,  Tsang Jiuh Wu ,  Ju Wang Hsu

发明人： Ming-Huan Tsai ,  Hun-Jan Tao ,  Tsang Jiuh Wu ,  Ju Wang Hsu

IPC分类号： H01L21302

CPC分类号： H01L21/76802 ,  H01L21/31116 ,  H01L21/31138 ,  H01L21/31144

摘要： An improved method of etching very small contact holes through dielectric layers used to separate conducting layers in multilevel integrated circuits formed on semiconductor substrates has been developed. The method uses bi-level ARC coatings in the resist structure and a unique combination of gaseous components in a plasma etching process which is used to dry develop the bi-level resist mask as well as etch through a silicon oxide dielectric layer. The gaseous components comprise a mixture of a fluorine containing gas, such as C4F8, C5F8, C4F6, CHF3 or similar species, an inert gas, such as helium or argon, an optional weak oxidant, such as CO or O2 or similar species, and a nitrogen source, such as N2, N2O, or NH3 or similar species. The patterned masking layer can be used to reliably etch contact holes in silicon oxide layers on semiconductor substrates, where the holes have diameters of about 0.1 micron or less.

摘要翻译： 已经开发了一种通过介电层蚀刻非常小的接触孔的改进方法，其用于在半导体衬底上形成的多层集成电路中分离导电层。 该方法在抗蚀剂结构中使用双层ARC涂层，并且在等离子体蚀刻工艺中使用气态组分的独特组合，其用于干燥显影双电平抗蚀剂掩模以及通过氧化硅介电层进行蚀刻。 气态组分包括含氟气体如C 4 F 8，C 5 F 8，C 4 F 6，CHF 3或类似物质，惰性气体如氦气或氩气，任选的弱氧化剂如CO或O 2或类似物质的混合物，以及 氮源，例如N 2，N 2 O或NH 3或类似物质。 图案化掩模层可用于可靠地蚀刻半导体衬底上的氧化硅层中的接触孔，其中孔的直径为约0.1微米或更小。

公开(公告)号：US06407002B1

公开(公告)日：2002-06-18

申请号：US09636583

申请日：2000-08-10

申请人： Li-Te Lin ,  Yuan-Hung Chiu ,  Ming-Huan Tsai ,  Hun-Jan Tao

发明人： Li-Te Lin ,  Yuan-Hung Chiu ,  Ming-Huan Tsai ,  Hun-Jan Tao

IPC分类号： H01L21302

CPC分类号： H01L21/31144 ,  H01L21/31138 ,  H01L21/76804 ,  H01L21/76829 ,  H01L21/76877

摘要： A method is provided for improving the tungsten, W-filling of hole openings in semiconductor substrates. This is accomplished by forming an opening—which can be used either as a contact or via hole—with a faceted entrance along with tapered side-walls. This combination of faceted entrance and tapered side-walls improves substantially the tungsten W-filling of contact/via holes in substrates without the formation of key-holes, thereby resulting in metal plugs of high electrical integrity and high reliability.

摘要翻译： 提供了一种提高半导体衬底中的开孔的钨，W填充的方法。 这可以通过形成开口来实现，该开口可以作为接触或通孔使用，与开口的入口以及锥形侧壁一起使用。 面形入口和锥形侧壁的这种组合基本上改善了衬底中的接触/通孔的钨W填充，而没有形成键孔，从而导致高电气完整性和高可靠性的金属插头。

公开(公告)号：US5824234A

公开(公告)日：1998-10-20

申请号：US725122

申请日：1996-10-02

申请人： Chon-Shin Jou ,  Ting-Sing Wang ,  Chun-Lin Chen ,  Ming-Huan Tsai ,  Ming-Ru Tsai

发明人： Chon-Shin Jou ,  Ting-Sing Wang ,  Chun-Lin Chen ,  Ming-Huan Tsai ,  Ming-Ru Tsai

IPC分类号： H01L21/311 ,  H01L21/60 ,  H01L21/00

CPC分类号： H01L21/31138 ,  H01L24/03 ,  H01L2224/0381 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/01029

摘要： The present invention provides a method for forming a bonding pad having a low contact resistance. The method includes steps of: a) forming a bonding pad structure on a substrate having a metal layer by forming a passivation layer over said metal layer and etching the passivation layer with a fluorine-containing gas by which a fluorine-containing layer is formed on a surface of said bonding pad structure; and b) removing the fluorine-containing layer for reducing a contact resistance of said bonding pad structure.

摘要翻译： 本发明提供一种形成接触电阻低的焊盘的方法。 该方法包括以下步骤：a）在具有金属层的衬底上形成焊盘结构，在所述金属层上形成钝化层，并用形成含氟层的含氟气体蚀刻钝化层 所述焊盘结构的表面; 以及b）除去所述含氟层以降低所述接合焊盘结构的接触电阻。

公开(公告)号：US20050092348A1

公开(公告)日：2005-05-05

申请号：US10701708

申请日：2003-11-05

申请人： Ju-Chien Chiang ,  Ming-Huan Tsai ,  Huan-Just Lin ,  Yuan-Hung Chiu ,  Hun-Jan Tao

发明人： Ju-Chien Chiang ,  Ming-Huan Tsai ,  Huan-Just Lin ,  Yuan-Hung Chiu ,  Hun-Jan Tao

IPC分类号： B08B3/08 ,  B08B3/12 ,  C11D3/39 ,  C11D7/08 ,  C11D11/00 ,  H01L21/306 ,  H01L21/311

CPC分类号： H01L21/02052 ,  B08B3/08 ,  B08B3/12 ,  C11D3/3947 ,  C11D7/08 ,  C11D11/0047 ,  H01L21/31122

摘要： The present invention provides aqueous compositions for cleaning integrated circuit substrates. Specifically, in the cleaning of an integrated circuit substrate, disclosed is a method for removing the by-products of the high-k dielectric dry etch process from the integrated circuit substrate, the method including: contacting the integrated circuit substrate with an aqueous composition including an amount, effective for the purpose of a (a) hydrogen fluoride, followed by (b) a mixture of hydrogen peroxide with a compound selected from the group consisting of ammonium hydroxide, hydrochloric acid and sulfuric acid.

摘要翻译： 本发明提供用于清洁集成电路基板的水性组合物。 具体地，在集成电路基板的清洗中，公开了从集成电路基板除去高介电常数干蚀刻工艺的副产物的方法，该方法包括：使集成电路基板与水性组合物接触，所述水性组合物包括 （a）氟化氢，其次是（b）过氧化氢与选自氢氧化铵，盐酸和硫酸的化合物的混合物的量。

公开(公告)号：US20050081781A1

公开(公告)日：2005-04-21

申请号：US10688045

申请日：2003-10-17

申请人： Huan-Just Lin ,  Ming-Huan Tsai ,  Li-Te Lin ,  Yuan-Hung Chiu ,  Han-Jan Tao

发明人： Huan-Just Lin ,  Ming-Huan Tsai ,  Li-Te Lin ,  Yuan-Hung Chiu ,  Han-Jan Tao

IPC分类号： C30B23/00 ,  C30B25/00 ,  C30B28/12 ,  C30B28/14 ,  H01L21/28 ,  H01L21/311 ,  H01L21/316 ,  H01L29/49 ,  H01L29/51

CPC分类号： H01L29/517 ,  H01L21/28079 ,  H01L21/28088 ,  H01L21/28194 ,  H01L21/31122 ,  H01L21/31645 ,  H01L29/495 ,  H01L29/4966 ,  H01L29/513

摘要： A fully dry etch method is described for removing a high k dielectric layer from a substrate without damaging the substrate and has a high selectivity with respect to a gate layer. The etch is comprised of BCl3, a fluorocarbon, and an inert gas. A low RF bias power is preferred. The method can also be used to remove an interfacial layer between the substrate and the high k dielectric layer. A HfO2 etch rate of 55 Angstroms per minute is achieved without causing a recess in a silicon substrate and with an etch selectivity to polysilicon of greater than 10:1. Better STI oxide divot control is also provided by this method. The etch through the high k dielectric layer may be performed in the same etch chamber as the etch process to form a gate electrode.

摘要翻译： 描述了用于从衬底去除高k电介质层而不损坏衬底并且相对于栅极层具有高选择性的全干蚀刻方法。 蚀刻由BCl 3 3，碳氟化合物和惰性气体组成。 低RF偏置功率是优选的。 该方法也可以用于去除衬底和高k电介质层之间的界面层。 实现了每分钟55埃的HfO 2/2蚀刻速率，而不会在硅衬底中产生凹陷，并且对多晶硅的蚀刻选择性大于10:1。 该方法也提供更好的STI氧化物控制。 通过高k介电层的蚀刻可以在与蚀刻工艺相同的蚀刻室中进行以形成栅电极。

公开(公告)号：US20050064721A1

公开(公告)日：2005-03-24

申请号：US10667013

申请日：2003-09-19

申请人： Ming-Huan Tsai ,  Ru-Chian Chiang ,  Hun-Jan Tao

发明人： Ming-Huan Tsai ,  Ru-Chian Chiang ,  Hun-Jan Tao

IPC分类号： H01L21/302 ,  H01L21/311 ,  H01L21/60

CPC分类号： H01L21/76897 ,  H01L21/31105 ,  H01L21/31116

摘要： A new method for fabricating a borderless interconnection in a semiconductor device is provided. During fabrication, the device includes an interlevel dielectric (ILD) layer, a metal silicide layer, and a stop layer disposed between the ILD and metal silicide layers. The stop layer may be formed of silicon nitride or silicon oxynitride, and the metal silicide layer may be a nickel silicide. The method includes etching the ILD layer to expose at least a portion of the stop layer and then performing a nitrogen plasma treatment on the exposed portion of the stop layer. After the treatment, the exposed portion of the stop layer is removed to provide the interconnection hole. Because of the plasma treatment, damage to the metal silicide underlying the stop layer will be minimized when the stop layer is removed.

摘要翻译： 提供了一种在半导体器件中制造无边界互连的新方法。 在制造期间，器件包括层间电介质（ILD）层，金属硅化物层和设置在ILD和金属硅化物层之间的阻挡层。 阻挡层可以由氮化硅或氮氧化硅形成，并且金属硅化物层可以是硅化镍。 该方法包括蚀刻ILD层以暴露停止层的至少一部分，然后在停止层的暴露部分上进行氮等离子体处理。 在处理之后，去除停止层的暴露部分以提供互连孔。 由于等离子体处理，当停止层被去除时，对停止层下面的金属硅化物的损坏将被最小化。

公开(公告)号：US06828205B2

公开(公告)日：2004-12-07

申请号：US10072798

申请日：2002-02-07

申请人： Ming-Huan Tsai ,  Ming-Jie Huang ,  Huan-Just Lin ,  Hun-Jan Tao

发明人： Ming-Huan Tsai ,  Ming-Jie Huang ,  Huan-Just Lin ,  Hun-Jan Tao

IPC分类号： H01L218222

CPC分类号： H01L21/31111 ,  H01L21/28123 ,  H01L21/32139

摘要： A method for using an isotropic wet etching process chemical process for trimming semiconductor feature sizes with improved critical dimension control including providing a hard mask overlying a substrate included in a semiconductor wafer said hard mask patterned for masking a portion of the substrate for forming a semiconductor feature according to an anisotropic plasma etching process; isotropically wet etching the hard mask to reduce a dimension of the hard mask prior to carrying out the anisotropic plasma etching process; and, anisotropically plasma etching a portion of the substrate not covered by the hard mask to form the semiconductor feature.

摘要翻译： 一种使用各向同性湿蚀刻工艺化学工艺的方法，用于修整具有改进的临界尺寸控制的半导体特征尺寸，包括提供覆盖在半导体晶片中的衬底的硬掩模，所述硬掩模被图案化以掩蔽用于形成半导体特征的衬底的一部分 根据各向异性等离子体蚀刻工艺; 在进行各向异性等离子体蚀刻工艺之前，均匀地湿式蚀刻硬掩模以减小硬掩模的尺寸; 并且各向异性等离子体蚀刻未被硬掩模覆盖的衬底的一部分以形成半导体特征。