公开(公告)号：US06610585B1

公开(公告)日：2003-08-26

申请号：US10083062

申请日：2002-02-26

申请人： Jeffrey S. Brown ,  Bryant C. Colwill ,  Terence B. Hook ,  Dennis Hoyniak

发明人： Jeffrey S. Brown ,  Bryant C. Colwill ,  Terence B. Hook ,  Dennis Hoyniak

IPC分类号： H01L21265

CPC分类号： H01L21/823878 ,  H01L21/2652 ,  H01L21/266 ,  H01L21/823481 ,  H01L21/823493 ,  H01L21/823892

摘要： A method of ion implantation is provided. The method comprising: providing a substrate; forming a masking image having a sidewall on the substrate; forming a blocking layer on the substrate and on the masking image; and performing a retrograde ion implant through the blocking layer into the substrate, wherein the blocking layer substantially blocks ions scattered at the sidewall of the masking layer.

公开(公告)号：US6026964A

公开(公告)日：2000-02-22

申请号：US920182

申请日：1997-08-25

申请人： Terence B. Hook ,  Jeffrey B. Johnson ,  Hon-Sum P. Wong

发明人： Terence B. Hook ,  Jeffrey B. Johnson ,  Hon-Sum P. Wong

IPC分类号： H01L27/146 ,  H01L31/0352 ,  H01L31/10 ,  H01L31/14 ,  H01L31/062

CPC分类号： H01L27/14643 ,  H01L27/14609 ,  H01L27/14689 ,  H01L31/0352

摘要： The present invention is a active pixel sensor cell and method of making and using the same. The active pixel sensor cell approximately doubles the available signal for a given quanta of light. The device of the present invention utilizes the holes produced by impinging photons in a active pixel sensor cell circuit. Two active pixel sensor cell circuits, an NFET circuit and PFET circuit are created for use with a photodiode. The NFET circuit captures electron current. The PFET circuit captures hole current. The sum of the currents is approximately double that of conventional active pixel sensor circuits using similarly sized photodiode regions.

摘要翻译： 本发明是一种有源像素传感器单元及其制造和使用方法。 有源像素传感器单元对于给定的光量大约使可用信号加倍。 本发明的器件利用通过在有源像素传感器单元电路中照射光子而产生的空穴。 创建两个有源像素传感器单元电路，NFET电路和PFET电路用于光电二极管。 NFET电路捕获电子电流。 PFET电路捕获空穴电流。 电流的总和大约是使用类似尺寸的光电二极管区域的传统有源像素传感器电路的总和的两倍。

公开(公告)号：US08916426B2

公开(公告)日：2014-12-23

申请号：US13431414

申请日：2012-03-27

申请人： William F. Clark, Jr. ,  Robert J. Gauthier, Jr. ,  Terence B. Hook ,  Junjun Li ,  Theodorus E. Standaert ,  Thomas A. Wallner

发明人： William F. Clark, Jr. ,  Robert J. Gauthier, Jr. ,  Terence B. Hook ,  Junjun Li ,  Theodorus E. Standaert ,  Thomas A. Wallner

IPC分类号： H01L21/338 ,  H01L29/66 ,  H01L21/8238 ,  H01L21/84

CPC分类号： H01L27/1211 ,  H01L21/7624 ,  H01L21/823821 ,  H01L21/845 ,  H01L27/0207 ,  H01L27/0262 ,  H01L27/0924 ,  H01L27/1203 ,  H01L29/66795 ,  H01L29/785

摘要： Device structures, design structures, and fabrication methods for passive devices that may be used as electrostatic discharge protection devices in fin-type field-effect transistor integrated circuit technologies. A device region is formed in a trench and is coupled with a handle wafer of a semiconductor-on-insulator substrate. The device region extends through a buried insulator layer of the semiconductor-on-insulator substrate toward a top surface of a device layer of the semiconductor-on-insulator substrate. The device region is comprised of lightly-doped semiconductor material. The device structure further includes a doped region formed in the device region and that defines a junction. A portion of the device region is laterally positioned between the doped region and the buried insulator layer of the semiconductor-on-insulator substrate. Another region of the device layer may be patterned to form fins for fin-type field-effect transistors.

摘要翻译： 无源器件的器件结构，设计结构和制造方法可用作鳍式场效应晶体管集成电路技术中的静电放电保护器件。 器件区域形成在沟槽中并且与绝缘体上半导体衬底的处理晶片耦合。 器件区域延伸穿过绝缘体上半导体衬底的掩埋绝缘体层朝向绝缘体上半导体衬底的器件层的顶表面。 器件区域由轻掺杂的半导体材料组成。 器件结构还包括形成在器件区域中并限定结的掺杂区域。 器件区域的一部分横向地位于绝缘体上半导体衬底的掺杂区域和掩埋绝缘体层之间。 可以对器件层的另一区域进行构图以形成翅片型场效应晶体管的鳍片。

公开(公告)号：US20140061792A1

公开(公告)日：2014-03-06

申请号：US13596409

申请日：2012-08-28

申请人： Huiming Bu ,  Terence B. Hook ,  Reinaldo A. Vega

发明人： Huiming Bu ,  Terence B. Hook ,  Reinaldo A. Vega

IPC分类号： H01L29/78 ,  H01L29/786

CPC分类号： H01L29/785 ,  H01L29/66795

摘要： A field effect transistor device includes a bulk semiconductor substrate, a fin arranged on the bulk semiconductor substrate, the fin including a source region, a drain region, and a channel region, a first shallow trench isolation (STI) region arranged on a portion of the bulk semiconductor substrate adjacent to the fin, a first recessed region partially defined by the first STI region and the channel region of the fin, and a gate stack arranged over the channel region of the fin, wherein a portion of the gate stack is partially disposed in the first recessed region.

摘要翻译： 场效应晶体管器件包括体半导体衬底，布置在体半导体衬底上的鳍，鳍包括源极区，漏极区和沟道区，布置在部分半导体衬底上的第一浅沟槽隔离（STI）区域 邻近翅片的体半导体衬底，由第一STI区域和鳍片的沟道区域部分限定的第一凹陷区域和布置在鳍片的沟道区域上的栅极堆叠，其中栅极叠层的一部分部分地 设置在第一凹陷区域中。

公开(公告)号：US08564074B2

公开(公告)日：2013-10-22

申请号：US13306621

申请日：2011-11-29

申请人： Terence B. Hook ,  Vijay Narayanan ,  Jay M. Shah ,  Melanie J. Sherony ,  Kenneth J. Stein ,  Helen H. Wang ,  Chendong Zhu

发明人： Terence B. Hook ,  Vijay Narayanan ,  Jay M. Shah ,  Melanie J. Sherony ,  Kenneth J. Stein ,  Helen H. Wang ,  Chendong Zhu

IPC分类号： H01L31/119

CPC分类号： H01L21/28247 ,  H01L21/28123 ,  H01L21/76224

摘要： A semiconductor device is disclosed. The semiconductor device includes a semiconductor substrate including: a high-K dielectric region; a blocking region disposed against at least one surface of the high-K dielectric region and adapted to form an oxidized layer in response to exposure to oxygen; and an oxygen rich region disposed against the blocking region such that the blocking region is interposed between the oxygen rich region and the high-K dielectric region.

摘要翻译： 公开了一种半导体器件。 半导体器件包括：半导体衬底，包括：高K电介质区域; 阻挡区域，其设置在所述高K电介质区域的至少一个表面上，并适于响应于暴露于氧气而形成氧化层; 以及设置在阻挡区域上的富氧区域，使得阻挡区域介于富氧区域和高K电介质区域之间。

公开(公告)号：US20130175594A1

公开(公告)日：2013-07-11

申请号：US13551714

申请日：2012-07-18

申请人： Veeraraghavan S. Basker ,  Kangguo Cheng ,  Bruce B. Doris ,  Terence B. Hook ,  Ali Khakifirooz ,  Pranita Kulkarni ,  Tenko Yamashita ,  Chun-Chen Yeh

发明人： Veeraraghavan S. Basker ,  Kangguo Cheng ,  Bruce B. Doris ,  Terence B. Hook ,  Ali Khakifirooz ,  Pranita Kulkarni ,  Tenko Yamashita ,  Chun-Chen Yeh

IPC分类号： H01L27/12 ,  H01L21/782

CPC分类号： H01L21/84 ,  H01L27/10861 ,  H01L27/1087 ,  H01L27/10873 ,  H01L27/10894 ,  H01L27/10897 ,  H01L27/1108 ,  H01L27/1116 ,  H01L27/1203 ,  H01L29/945

摘要： An integrated circuit comprising an N+ type layer, a buffer layer arranged on the N+ type layer; a P type region formed on with the buffer layer; an insulator layer overlying the N+ type layer, a silicon layer overlying the insulator layer, an embedded RAM FET formed in the silicon layer and connected with a conductive node of a trench capacitor that extends into the N+ type layer, the N+ type layer forming a plate electrode of the trench capacitor, a first contact through the silicon layer and the insulating layer and electrically connecting to the N+ type layer, a first logic RAM FET formed in the silicon layer above the P type region, the P type region functional as a P-type back gate of the first logic RAM FET, and a second contact through the silicon layer and the insulating layer and electrically connecting to the P type region.

公开(公告)号：US20120326752A1

公开(公告)日：2012-12-27

申请号：US13167826

申请日：2011-06-24

申请人： Terence B. Hook ,  Jeffrey B. Johnson

发明人： Terence B. Hook ,  Jeffrey B. Johnson

IPC分类号： H03K5/24 ,  H01L29/78 ,  G06F17/50

CPC分类号： G06F17/5068 ,  H01L23/544 ,  H01L29/1083 ,  H01L29/7833 ,  H01L2223/5444 ,  H03K3/84

摘要： Disclosed are a design method and structure for a transistor having a relatively large threshold voltage (Vt) variation range due to exacerbated random dopant fluctuation (RDF). Exacerbated RDF and, thereby a relatively large Vt variation range, is achieved through the use of complementary doping in one or more transistor components and/or through lateral dopant non-uniformity between the channel region and any halo regions. Also disclosed are a design method and structure for a random number generator, which incorporates multiple pairs of essentially identical transistors having such a large Vt variation and which relies on Vt mismatch in pairs of those the transistors to generate a multi-bit output (e.g., a unique identifier for a chip or a secret key). By widening the Vt variation range of the transistors in the random number generator, detecting Vt mismatch between transistors becomes more likely and the resulting multi-bit output will be more stable.

摘要翻译： 公开了由于加剧的随机掺杂剂波动（RDF）而具有相对大的阈值电压（Vt）变化范围的晶体管的设计方法和结构。 通过在一个或多个晶体管组件中使用互补掺杂和/或通过沟道区域和任何晕圈区域之间的横向掺杂剂不均匀性来实现RDF的恶化，从而达到相对较大的Vt变化范围。 还公开了一种用于随机数发生器的设计方法和结构，该方法和结构包括具有如此大的Vt变化的多对基本相同的晶体管，并且其依赖于晶体管对的Vt失配以产生多位输出（例如， 芯片或密钥的唯一标识符）。 通过扩大随机数发生器中的晶体管的Vt变化范围，检测晶体管之间的Vt失配变得更可能，并且所得到的多位输出将更加稳定。

公开(公告)号：US20120018812A1

公开(公告)日：2012-01-26

申请号：US12840689

申请日：2010-07-21

申请人： Brent A. Anderson ,  Terence B. Hook

发明人： Brent A. Anderson ,  Terence B. Hook

IPC分类号： H01L27/088 ,  G06F17/50 ,  H01L21/8234 ,  H01L29/78

CPC分类号： H01L29/78696 ,  G06F17/505 ,  G06F2217/78 ,  H01L29/4908

摘要： Methods and systems evaluate an integrated circuit design for power consumption balance and performance balance, using a computerized device. Based on this process of evaluating the integrated circuit, the methods and systems can identify first sets of integrated circuit transistor structures within the integrated circuit design that need reduced power leakage and second sets of integrated circuit transistor structures that need higher performance to achieve the desired power consumption balance and performance balance. With this, the methods and systems alter the integrated circuit design to include implantation of a first dopant into a substrate before a gate insulator formation for the first sets of integrated circuit transistor structures; and alter the integrated circuit design to include implantation of a second dopant into the substrate before a gate insulator formation for the second sets of integrated circuit transistor structures. The method and system then output the altered integrated circuit design from the computerized device and/or manufactures the device according to the altered integrated circuit design.

摘要翻译： 方法和系统使用计算机化设备评估功耗平衡和性能平衡的集成电路设计。 基于对集成电路进行评估的方法，该方法和系统可以识别集成电路设计中需要减少功率泄漏的第一组集成电路晶体管结构，并且需要更高性能的第二组集成电路晶体管结构来实现所需功率 消费平衡和业绩平衡。 由此，方法和系统改变了集成电路设计，包括在用于第一组集成电路晶体管结构的栅极绝缘体形成之前将第一掺杂剂注入到衬底中; 并且改变集成电路设计以在第二组集成电路晶体管结构的栅极绝缘体形成之前将第二掺杂剂注入到衬底中。 该方法和系统然后从计算机化设备输出改变的集成电路设计和/或根据改变的集成电路设计制造设备。

公开(公告)号：US07879650B2

公开(公告)日：2011-02-01

申请号：US12002807

申请日：2007-12-19

申请人： Terence B. Hook ,  Anda C. Mocuta ,  Jeffrey W. Sleight ,  Anthony K. Stamper

发明人： Terence B. Hook ,  Anda C. Mocuta ,  Jeffrey W. Sleight ,  Anthony K. Stamper

IPC分类号： H01L21/8238

CPC分类号： H01L21/84 ,  H01L21/823807 ,  H01L21/823878 ,  H01L27/0251 ,  H01L27/0629 ,  H01L27/1203 ,  H01L27/1207

摘要： In a method of fabricating a CMOS structure, a bulk device can be formed in a first region in conductive communication with an underlying bulk region of the substrate. A first gate conductor may overlie the first region. An SOI device can be formed which has a source drain conduction path in a SOI layer, i.e., a semiconductor layer that is separated from the bulk region by a buried dielectric region. The crystal orientations of the SOI layer and the bulk region can be different. A first diode can be formed in a second region of the substrate in conductive communication with the bulk region. The first diode may be connected in a reverse-biased orientation to a first gate conductor above the SOI layer, such that a voltage on the gate conductor that exceeds the breakdown voltage can be discharged through the first diode to the bulk region of the substrate. A second diode may be formed in a third region of the substrate in conductive communication with the bulk region. The second diode may be connected in a reverse-biased orientation to a source region or a drain region of an NFET.

摘要翻译： 在制造CMOS结构的方法中，本体器件可以形成在与衬底的下面的主体区域导电连通的第一区域中。 第一栅极导体可以覆盖在第一区域上。 可以形成在SOI层中具有源极漏极传导路径的SOI器件，即通过掩埋电介质区域与本体区域分离的半导体层。 SOI层和体区的晶体取向可以不同。 第一二极管可以形成在衬底的与体区导电连通的第二区域中。 第一二极管可以以反向偏置的方式连接到SOI层上方的第一栅极导体，使得超过击穿电压的栅极导体上的电压可以通过第一二极管放电到衬底的主体区域。 第二二极管可以形成在衬底的与体区导电连通的第三区域中。 第二二极管可以以反向偏置的方式连接到NFET的源极区域或漏极区域。

公开(公告)号：US07709365B2

公开(公告)日：2010-05-04

申请号：US11551959

申请日：2006-10-23

申请人： Wilfried Haensch ,  Terence B. Hook ,  Louis C. Hsu ,  Rajiv V. Joshi ,  Werner Rausch

发明人： Wilfried Haensch ,  Terence B. Hook ,  Louis C. Hsu ,  Rajiv V. Joshi ,  Werner Rausch

IPC分类号： H01L21/22 ,  H01L21/38

CPC分类号： H01L29/78 ,  H01L21/823892 ,  H01L27/0928

摘要： A method for forming a CMOS well structure including forming a plurality of first conductivity type wells over a substrate, each of the plurality of first conductivity type wells formed in a respective opening in a first mask. A cap is formed over each of the first conductivity type wells, and the first mask is removed. Sidewall spacers are formed on sidewalls of each of the first conductivity type wells. A plurality of second conductivity type wells are formed, each of the plurality of second conductivity type wells are formed between respective first conductivity type wells. A plurality of shallow trench isolations are formed between the first conductivity type wells and second conductive type wells. The plurality of first conductivity type wells are formed by a first selective epitaxial growth process, and the plurality of second conductivity type wells are formed by a second selective epitaxial growth process.

摘要翻译： 一种用于形成CMOS阱结构的方法，包括在衬底上形成多个第一导电类型阱，所述多个第一导电类型阱中的每一个形成在第一掩模中的相应开口中。 在每个第一导电类型的阱上形成盖，并且去除第一掩模。 在每个第一导电类型的孔的侧壁上形成侧壁间隔物。 形成多个第二导电型阱，多个第二导电型阱中的每一个形成在相应的第一导电型阱之间。 在第一导电型阱和第二导电类型阱之间形成多个浅沟槽隔离。 通过第一选择性外延生长工艺形成多个第一导电型阱，并且通过第二选择性外延生长工艺形成多个第二导电型阱。