NVM PMOS-cell with one erased and two programmed states
    31.
    发明授权
    NVM PMOS-cell with one erased and two programmed states 有权
    NVM PMOS单元具有一个擦除和两个编程状态

    公开(公告)号:US07113427B1

    公开(公告)日:2006-09-26

    申请号:US11076711

    申请日:2005-03-09

    Abstract: NVM cell for storing three levels of charge: one erased and two programmed states. The cell comprises a transistor structure providing a gate current versus gate voltage curve having a shape with a flat region or a second peak. To provide such a structure, one embodiment combines two parallel transistors having different threshold voltages, and another embodiment uses one transistor with variable doping. The gate current curve provides two programming zones. Programming the first state includes applying a voltage across a channel, ramping up a gate voltage in the first programming zone, followed by ramping it back down. Programming the second state comprises applying a voltage across a channel, ramping up a gate voltage past the first programming zone and into the second programming zone, followed by ramping it back down. Ramping the voltage back down may optionally be preceded by turning off the voltage across the channel.

    Abstract translation: 用于存储三个电荷电平的NVM单元:一个擦除和两个编程状态。 该单元包括提供具有平坦区域或第二峰值的形状的栅极电流对栅极电压曲线的晶体管结构。 为了提供这样的结构,一个实施例组合了具有不同阈值电压的两个并联晶体管,另一实施例使用一个具有可变掺杂的晶体管 栅极电流曲线提供两个编程区域。 对第一状态进行编程包括在一个通道上施加电压,使第一个编程区中的栅极电压升高,然后将其向下斜坡。 对第二状态进行编程包括在通道上施加电压,将栅极电压升高到第一编程区并进入第二编程区,然后将其向下斜坡。 可以选择先将电压降低,然后关闭通道上的电压。

    High-speed photon detector and method of forming the detector
    32.
    发明授权
    High-speed photon detector and method of forming the detector 有权
    高速光子探测器及形成探测器的方法

    公开(公告)号:US07057174B1

    公开(公告)日:2006-06-06

    申请号:US10355904

    申请日:2003-01-30

    CPC classification number: H01L31/08

    Abstract: A photon detector capable of detecting gigahertz frequency optical signals utilizes a layer of photonic material that is formed adjacent to the coil of an inductor. When a pulsed light source is applied to the layer of photonic material, the photonic material generates eddy currents that alter the magnetic flux of the inductor. The signals can then be detected by detecting the change in the magnetic flux.

    Abstract translation: 能够检测千兆赫兹光信号的光子检测器利用与电感线圈相邻形成的光子材料层。 当脉冲光源被施加到光子材料层时,光子材料产生改变电感器的磁通量的涡流。 然后可以通过检测磁通量的变化来检测信号。

    On-chip power inductor
    39.
    发明授权
    On-chip power inductor 有权
    片上功率电感

    公开(公告)号:US07875955B1

    公开(公告)日:2011-01-25

    申请号:US11713921

    申请日:2007-03-05

    Abstract: An on-chip inductor structure for a DC-DC power regulator circuit merges the switching transistor metallization with the inductor. Thick top level conductor metal that is used to strap the transistor array and to lower its on-state resistance is also used to extend the power inductor into the transistor array. Thus, the structure includes three basic components: a power inductor that spirals around the transistor array, the transistor array itself, and the transistor array metallization that is used to form a distributed inductance situated over the transistor array.

    Abstract translation: 用于DC-DC功率调节器电路的片上电感器结构将开关晶体管金属化与电感器并入。 用于绑定晶体管阵列并降低其导通电阻的厚顶级导体金属也用于将功率电感器扩展到晶体管阵列中。 因此,该结构包括三个基本部件:围绕晶体管阵列螺旋的功率电感器,晶体管阵列本身以及用于形成位于晶体管阵列上方的分布式电感器的晶体管阵列金属化。

    Self-protecting transistor array
    40.
    发明授权
    Self-protecting transistor array 有权
    自保护晶体管阵列

    公开(公告)号:US07217966B1

    公开(公告)日:2007-05-15

    申请号:US11060877

    申请日:2005-02-18

    CPC classification number: H01L27/0266 H01L29/78

    Abstract: A transistor array is self-protected from an electrostatic discharge (ESD) event which can cause localized ESD damage by integrating an ESD protection device into the transistor array. The ESD protection device operates as a transistor during normal operating conditions, and provides a low-resistance current path during an ESD event.

    Abstract translation: 晶体管阵列可以通过将ESD保护器件集成到晶体管阵列中而免受静电放电(ESD)事件的影响,从而导致局部ESD损坏。 ESD保护装置在正常操作条件下作为晶体管工作,并且在ESD事件期间提供低电阻电流路径。

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