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176 条记录 (耗时 0.028 秒)

    Differential non-linearity correction scheme
    31.
    发明授权
    Differential non-linearity correction scheme 有权
    差分非线性校正方案

    公开(公告)号：US06215428B1

    公开(公告)日：2001-04-10

    申请号：US09170944

    申请日：1998-10-13

    申请人： Eric R. Fossum

    发明人： Eric R. Fossum

    IPC分类号： H03M106

    CPC分类号： H03M1/1061 ,  H03M1/804

    摘要： Differential non-linearity errors in an A/D converter are corrected by an analog system. The system produces different analog voltages which are used to correct the input voltage to the capacitor. The input voltage is changed by an amount which is effective to correct the CAV to be the same as it would have been if the DNL error had not occurred.

    摘要翻译： A / D转换器中的微分非线性误差由模拟系统校正。 该系统产生不同的模拟电压，用于校正电容器的输入电压。 输入电压的改变量可以有效地将CAV修正为与没有发生DNL错误时的相同。

    Active pixel sensor with current mode readout
    32.
    发明授权
    Active pixel sensor with current mode readout 有权
    有源像素传感器，具有电流模式读数

    公开(公告)号：US06194696B1

    公开(公告)日：2001-02-27

    申请号：US09265936

    申请日：1999-03-10

    申请人： Eric R. Fossum ,  Alexander Krymski ,  Barmak Mansoorian

    发明人： Eric R. Fossum ,  Alexander Krymski ,  Barmak Mansoorian

    IPC分类号： H01L2700

    CPC分类号： H04N5/378 ,  H04N5/3575

    摘要： A current mode device for an active pixel sensor includes a voltage to current converter which includes an operation that occurs inside a source follower. The device operates to draw no current while the current is incoming. The device uses two stages of double sampling—one before the current-mode op amp and one after.

    摘要翻译： 用于有源像素传感器的电流模式器件包括电压 - 电流转换器，其包括在源极跟随器内发生的操作。 当电流进入时，该装置工作时无需画出电流。 该器件使用两个阶段的双采样 - 一个在电流模式运放和一个之后。

    Integrated sensor with frame memory and programmable resolution for light adaptive imaging
    34.
    发明授权
    Integrated sensor with frame memory and programmable resolution for light adaptive imaging 有权
    具有帧存储器和可编程分辨率的集成传感器，用于光自适应成像

    公开(公告)号：US6057539A

    公开(公告)日：2000-05-02

    申请号：US323556

    申请日：1999-06-01

    申请人： Zhimim Zhou ,  Eric R. Fossum ,  Bedabrata Pain

    发明人： Zhimim Zhou ,  Eric R. Fossum ,  Bedabrata Pain

    IPC分类号： G11C27/04 ,  H04N5/347 ,  H04N5/365 ,  H04N5/369 ,  H04N5/374 ,  H01J40/14

    CPC分类号： H04N5/347 ,  G11C27/04 ,  H04N5/3743

    摘要： An image sensor operable to vary the output spatial resolution according to a received light level while maintaining a desired signal-to-noise ratio. Signals from neighboring pixels in a pixe patch with an adjustable size are added to increase both the image brightness and signal-to-noise ratio. One embodiment comprises a sensor array for receiving input signals, a frame memory array for temporarily storing a full frame, and an array of self-calibration column integrators for uniform column-parallel signal summation. The column integrators are capable of substantially canceling fixed pattern noise.

    摘要翻译： 一种图像传感器，其可操作以根据接收的光电平改变输出空间分辨率，同时保持期望的信噪比。 增加了具有可调大小的像素补片中相邻像素的信号，以增加图像亮度和信噪比。 一个实施例包括用于接收输入信号的传感器阵列，用于临时存储全帧的帧存储器阵列，以及用于统一的列并行信号求和的自校准列积分器的阵列。 列积分器能够基本上消除固定模式噪声。

    Digital parallel processor array for optimum path planning
    36.
    发明授权
    Digital parallel processor array for optimum path planning 失效
    数字并行处理器阵列，实现最佳路径规划

    公开(公告)号：US5548773A

    公开(公告)日：1996-08-20

    申请号：US42486

    申请日：1993-03-30

    申请人： Sabrina E. Kemeny ,  Eric R. Fossum ,  Robert H. Nixon

    发明人： Sabrina E. Kemeny ,  Eric R. Fossum ,  Robert H. Nixon

    IPC分类号： G06F17/50 ,  G06F15/00 ,  G06F15/20

    CPC分类号： G06F17/509 ,  G06Q30/0283

    摘要： The invention computes the optimum path across a terrain or topology represented by an array of parallel processor cells interconnected between neighboring cells by links extending along different directions to the neighboring cells. Such an array is preferably implemented as a high-speed integrated circuit. The computation of the optimum path is accomplished by, in each cell, receiving stimulus signals from neighboring cells along corresponding directions, determining and storing the identity of a direction along which the first stimulus signal is received, broadcasting a subsequent stimulus signal to the neighboring cells after a predetermined delay time, whereby stimulus signals propagate throughout the array from a starting one of the cells. After propagation of the stimulus signals throughout the array, a master processor traces back from a selected destination cell to the starting cell along an optimum path of the cells in accordance with the identity of the directions stored in each of the cells.

    摘要翻译： 本发明通过沿着不同方向向相邻小区延伸的链路计算由相邻小区之间互连的并行处理单元的阵列所表示的地形或拓扑的最佳路径。 这样的阵列优选地被实现为高速集成电路。 最佳路径的计算是通过在每个小区中从沿着相应方向的相邻小区接收刺激信号来实现的，确定并存储接收第一刺激信号的方向的身份，将后续的刺激信号广播到相邻小区 在预定的延迟时间之后，由此刺激信号从整个阵列中的起始单元传播。 在整个阵列中激励信号传播之后，主处理器根据存储在每个单元中的方向的身份沿着单元的最佳路径从选定的目的地单元追溯到起始单元。

    Trench-defined charge-coupled device
    37.
    发明授权
    Trench-defined charge-coupled device 失效
    沟槽定义的电荷耦合器件

    公开(公告)号：US5055900A

    公开(公告)日：1991-10-08

    申请号：US419904

    申请日：1989-10-11

    申请人： Eric R. Fossum ,  Sabrina E. Kemeny

    发明人： Eric R. Fossum ,  Sabrina E. Kemeny

    IPC分类号： H01L29/762 ,  H01L21/339 ,  H01L27/148 ,  H01L29/423 ,  H01L29/768

    CPC分类号： H01L29/768 ,  H01L27/14831 ,  H01L29/42396

    摘要： A charge-coupled device (CCD) is formed by first defining relatively deep trenches having relatively small lateral dimensions in the surface of a silicon bulk region. A relatively thin silicon dioxide layer is formed over the silicon surface and inside each trench to cover the internal surfaces thereof. Finally, respective conducting electrode layers are formed over each trench covering the silicon dioxide layer within the trench. Such a CCD structure provides improved packing density and versatility of function over a conventional surface electrode CCD structures. When used in an image-sensing device, the trench-defined CCD structure provides improved quantum efficiency, owing to the deeper potential wells which may be formed in such structures for capturing photogenerated charge carriers.

    摘要翻译： 电荷耦合器件（CCD）通过首先在硅体区域的表面中限定具有相对小的横向尺寸的相对较深的沟槽而形成。 在硅表面和每个沟槽内部形成相对薄的二氧化硅层以覆盖其内表面。 最后，在覆盖沟槽内的二氧化硅层的每个沟槽上形成各个导电电极层。 这样的CCD结构提供了改进的堆积密度和功能与常规表面电极CCD结构的通用性。 当在图像感测装置中使用时，由于在用于捕获光生电荷载体的这种结构中可能形成的较深的势阱，沟槽限定的CCD结构提供了改进的量子效率。

    DIGITAL INTEGRATION SENSOR
    38.
    发明申请
    DIGITAL INTEGRATION SENSOR 审中-公开
    数字整合传感器

    公开(公告)号：US20120281126A1

    公开(公告)日：2012-11-08

    申请号：US13441906

    申请日：2012-04-08

    申请人： Eric R. Fossum

    发明人： Eric R. Fossum

    IPC分类号： H04N5/335

    CPC分类号： H04N5/23251 ,  H04N5/23258 ,  H04N5/23277 ,  H04N5/2355 ,  H04N5/35572

    摘要： Multiple scans of a digital integration image sensor are combined to form an output image. The sensor scans or portions thereof may be positionally-shifted relative to one another, and may be acquired in uniform or non-uniform exposure intervals. Selected pixels within at least one of the scans may be excluded from the combination. The scans may also be non-uniformly weighted prior to being combined, with the scan weighting profile corresponding to the scan order.

    摘要翻译： 数字积分图像传感器的多次扫描被组合以形成输出图像。 传感器扫描或其部分可以相对于彼此位置偏移，并且可以以均匀或不均匀的曝光间隔获取。 可以从组合中排除至少一个扫描内的所选像素。 在组合之前，扫描也可以被非均匀加权，扫描加权轮廓对应于扫描顺序。