公开(公告)号：US20090194824A1

公开(公告)日：2009-08-06

申请号：US12144281

申请日：2008-06-23

申请人： Frank Wirbeleit

发明人： Frank Wirbeleit

IPC分类号： H01L21/8244

CPC分类号： H01L27/11 ,  H01L29/7841

摘要： By providing a body controlled double channel transistor, increased functionality in combination with enhanced stability may be accomplished. For instance, flip flop circuits usable for static RAM cells may be formed on the basis of the body controlled double channel transistor, thereby reducing the number of transistors required per cell, which may result in increased information density.

摘要翻译： 通过提供体控双通道晶体管，可以实现与增强的稳定性相结合的增加的功能。 例如，可以基于体控双通道晶体管形成可用于静态RAM单元的触发器电路，从而减少每个单元所需的晶体管数量，这可能导致信息密度增加。

公开(公告)号：US07442971B2

公开(公告)日：2008-10-28

申请号：US11045177

申请日：2005-01-28

申请人： Frank Wirbeleit ,  Manfred Horstmann ,  Christian Hobert

发明人： Frank Wirbeleit ,  Manfred Horstmann ,  Christian Hobert

IPC分类号： H01L31/112

CPC分类号： H01L29/105 ,  G11C11/412 ,  H01L27/11 ,  H01L29/7838

摘要： By providing a self-biasing semiconductor switch, an SRAM cell having a reduced number of individual active components may be realized. In particular embodiments, the self-biasing semiconductor device may be provided in the form of a double channel field effect transistor that allows the formation of an SRAM cell with less than six transistor elements and, in preferred embodiments, with as few as two individual transistor elements.

摘要翻译： 通过提供自偏压半导体开关，可以实现具有减少数量的各个有源元件的SRAM单元。 在特定实施例中，自偏置半导体器件可以以双通道场效应晶体管的形式提供，其允许形成具有小于六个晶体管元件的SRAM单元，并且在优选实施例中，具有少至两个单独的晶体管 元素。

公开(公告)号：US20080242040A1

公开(公告)日：2008-10-02

申请号：US11942400

申请日：2007-11-19

申请人： Frank Wirbeleit ,  Rolf Stephan ,  Manfred Horstmann

发明人： Frank Wirbeleit ,  Rolf Stephan ,  Manfred Horstmann

IPC分类号： H01L21/336

CPC分类号： H01L21/28123 ,  H01L29/66545 ,  H01L29/6659

摘要： A method of forming a semiconductor structure comprises providing a semiconductor substrate. A feature is formed over the substrate. The feature is substantially homogeneous in a lateral direction. A first ion implantation process adapted to introduce first dopant ions into at least one portion of the substrate adjacent the feature is performed. The length of the feature in the lateral direction is reduced. After the reduction of the length of the feature, a second ion implantation process adapted to introduce second dopant ions into at least one portion of the substrate adjacent the feature is performed. The feature may be a gate electrode of a field effect transistor to be formed over the semiconductor substrate.

摘要翻译： 形成半导体结构的方法包括提供半导体衬底。 在衬底上形成特征。 该特征在横向上基本上是均匀的。 执行适于将第一掺杂剂离子引入邻近该特征的衬底的至少一部分中的第一离子注入工艺。 横向的特征长度减小。 在特征的长度减小之后，执行适于将第二掺杂剂离子引入邻近该特征的衬底的至少一部分中的第二离子注入工艺。 该特征可以是要形成在半导体衬底上的场效应晶体管的栅电极。

公开(公告)号：US20080158541A1

公开(公告)日：2008-07-03

申请号：US11856799

申请日：2007-09-18

申请人： Frank Wirbeleit

发明人： Frank Wirbeleit

IPC分类号： G01B11/16

CPC分类号： G01N21/1717 ,  G01N21/47 ,  G01N2021/1719 ,  G01N2021/213

摘要： By performing optical measurements and evaluating the optical response of an appropriately prepared measurement site, stress-related characteristics, such as intrinsic stress of dielectric layers, may be evaluated due to the dependency of the optical response on stress-induced modifications of the charge carrier mobility of a conductive layer provided below the dielectric layer probed by an optical signal. Consequently, inline measurement results may be obtained in a highly efficient manner, thereby providing the potential for monitoring complex stress engineering strategies during a manufacturing sequence for forming microstructure devices.

摘要翻译： 通过进行光学测量和评估适当制备的测量点的光学响应，可以评估应力相关特性，例如介电层的固有应力，这是由于光响应对应力诱导的电荷载流子迁移的修饰的依赖性 设置在由光信号探测的电介质层下方的导电层。 因此，可以以高效的方式获得在线测量结果，从而提供在用于形成微结构器件的制造顺序期间监测复杂应力工程策略的潜力。

公开(公告)号：US20070176246A1

公开(公告)日：2007-08-02

申请号：US11484295

申请日：2006-07-11

申请人： Frank Wirbeleit ,  Martin Majer

发明人： Frank Wirbeleit ,  Martin Majer

IPC分类号： H01L29/76

CPC分类号： H01L27/11 ,  G11C11/412 ,  H01L29/105

摘要： By providing a self-biasing semiconductor switch, an SRAM cell having a reduced number of individual active components may be realized. In particular embodiments, the self-biasing semiconductor device may be provided in the form of a double channel field effect transistor that allows the formation of an SRAM cell with less than six transistor elements and in preferred embodiments with as few as two individual transistor elements.

摘要翻译： 通过提供自偏压半导体开关，可以实现具有减少数量的各个有源元件的SRAM单元。 在特定实施例中，自偏置半导体器件可以以双通道场效应晶体管的形式提供，其允许形成具有小于六个晶体管元件的SRAM单元，并且在优选实施例中可以使用少至两个单独的晶体管元件。

公开(公告)号：US20070072380A1

公开(公告)日：2007-03-29

申请号：US11235791

申请日：2005-09-26

申请人： Frank Wirbeleit ,  Linda Black ,  Igor Peidous

发明人： Frank Wirbeleit ,  Linda Black ,  Igor Peidous

IPC分类号： H01L21/336 ,  H01L21/3205 ,  H01L21/4763

CPC分类号： H01L27/1203 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823878 ,  H01L21/84 ,  H01L29/0649 ,  H01L29/1037 ,  H01L29/66636 ,  H01L29/66772 ,  H01L29/7848 ,  H01L29/7849 ,  H01L29/78654

摘要： Methods for fabricating a stressed MOS device is provided. One method comprises the steps of providing a monocrystalline semiconductor substrate having a surface and a channel abutting the surface. A gate electrode having a first edge and a second edge is formed overlying the monocrystalline semiconductor substrate. The substrate is anisotropically etched to form a first recess aligned with the first edge and a second recess aligned with the second edge. The substrate is further isotropically etched to form a third recess in the substrate extending beneath the channel. The third recess is filled with an expanding material to exert an upward force on the channel and the first and second recesses are filled with a contact material. Conductivity determining ions are implanted into the contact material to form a source region and a drain region aligned with the first and second edges, respectively.

摘要翻译： 提供制造应力MOS器件的方法。 一种方法包括提供具有表面和邻接表面的通道的单晶半导体衬底的步骤。 具有第一边缘和第二边缘的栅电极形成在单晶半导体衬底上。 基板被各向异性蚀刻以形成与第一边缘对准的第一凹部和与第二边缘对准的第二凹部。 衬底被进一步各向同性蚀刻以在通道下延伸的衬底中形成第三凹槽。 第三凹部填充有膨胀材料以在通道上施加向上的力，并且第一和第二凹部填充有接触材料。 电导率确定离子被注入到接触材料中以分别形成与第一和第二边缘对准的源极区域和漏极区域。

公开(公告)号：US20060003510A1

公开(公告)日：2006-01-05

申请号：US11112498

申请日：2005-04-22

申请人： Thorsten Kammler ,  Martin Gerhardt ,  Frank Wirbeleit

发明人： Thorsten Kammler ,  Martin Gerhardt ,  Frank Wirbeleit

IPC分类号： H01L21/8234 ,  H01L21/336

CPC分类号： H01L21/823807 ,  H01L21/26506 ,  H01L21/7624 ,  H01L21/84 ,  H01L29/0649 ,  H01L29/1054 ,  H01L29/665 ,  H01L29/6659 ,  H01L29/66772 ,  H01L29/7843 ,  Y10S438/938

摘要： A dislocation region is formed by implanting a light inert species, such as hydrogen, to a specified depth and with a high concentration, and by heat treating the inert species to create “nano” bubbles, which enable a certain mechanical decoupling to underlying device regions, thereby allowing a more efficient creation of strain that is induced by an external stress-generating source. In this way, strain may be created in a channel region of a field effect transistor by, for instance, a stress layer or sidewall spacers formed in the vicinity of the channel region.

公开(公告)号：US08642420B2

公开(公告)日：2014-02-04

申请号：US13219331

申请日：2011-08-26

申请人： Stefan Flachowsky ,  Frank Wirbeleit ,  Matthias Kessler ,  Ricardo P. Mikalo

发明人： Stefan Flachowsky ,  Frank Wirbeleit ,  Matthias Kessler ,  Ricardo P. Mikalo

IPC分类号： H01L21/8238

CPC分类号： H01L21/823807 ,  H01L21/823814

摘要： A method of fabricating a semiconductor device structure begins by forming a layer of oxide material overlying a first gate structure having a first silicon nitride cap and overlying a second gate structure having a second silicon nitride cap. The first gate structure corresponds to a p-type transistor to be fabricated, and the second gate structure corresponds to an n-type transistor to be fabricated. The method continues by performing a tilted ion implantation procedure to implant ions of an impurity species in a channel region of semiconductor material underlying the first gate structure, during which an ion implantation mask protects the second gate structure. Thereafter, the ion implantation mask and the layer of oxide material are removed, and regions of epitaxial semiconductor material are formed corresponding to source and drain regions for the first gate structure. Thereafter, the first silicon nitride cap and the second silicon nitride cap are removed.

摘要翻译： 制造半导体器件结构的方法开始于形成覆盖具有第一氮化硅帽的第一栅极结构的氧化物层，并且覆盖具有第二氮化硅帽的第二栅极结构。 第一栅极结构对应于要制造的p型晶体管，并且第二栅极结构对应于待制造的n型晶体管。 该方法通过执行倾斜离子注入程序来将杂质物质的离子注入到第一栅极结构下面的半导体材料的沟道区域中，在此期间离子注入掩模保护第二栅极结构。 此后，去除离子注入掩模和氧化物层，并且对应于第一栅极结构的源区和漏区形成外延半导体材料的区域。 此后，去除第一氮化硅盖和第二氮化硅盖。

公开(公告)号：US08507953B2

公开(公告)日：2013-08-13

申请号：US12956291

申请日：2010-11-30

申请人： Frank Wirbeleit

发明人： Frank Wirbeleit

IPC分类号： H01L27/118

CPC分类号： H01L27/11 ,  H01L29/7841

摘要： By providing a body controlled double channel transistor, increased functionality in combination with enhanced stability may be accomplished. For instance, flip flop circuits usable for static RAM cells may be formed on the basis of the body controlled double channel transistor, thereby reducing the number of transistors required per cell, which may result in increased information density.

摘要翻译： 通过提供体控双通道晶体管，可以实现与增强的稳定性相结合的增加的功能。 例如，可以基于体控双通道晶体管形成可用于静态RAM单元的触发器电路，从而减少每个单元所需的晶体管数量，这可能导致信息密度增加。

公开(公告)号：US08298924B2

公开(公告)日：2012-10-30

申请号：US11866491

申请日：2007-10-03

申请人： Maciej Wiatr ,  Frank Wirbeleit ,  Andy Wei ,  Andreas Gehring

发明人： Maciej Wiatr ,  Frank Wirbeleit ,  Andy Wei ,  Andreas Gehring

IPC分类号： H01L27/092 ,  H01L21/04

CPC分类号： H01L21/823864 ,  H01L21/823835 ,  H01L27/092 ,  H01L29/665 ,  H01L29/6653 ,  H01L29/6656 ,  H01L29/7843

摘要： By removing an outer spacer of a transistor element, used for the formation of highly complex lateral dopant profiles, prior to the formation of metal silicide, employing a wet chemical etch process, it is possible to position a stressed contact liner layer more closely to the channel region, thereby allowing a highly efficient stress transfer mechanism for creating a corresponding strain in the channel region, without affecting circuit elements in the P-type regions.

摘要翻译： 通过去除用于形成高度复杂的横向掺杂剂分布的晶体管元件的外部间隔物，在形成金属硅化物之前，采用湿化学蚀刻工艺，可以将应力接触衬垫层更靠近 从而允许用于在沟道区域中产生相应应变的高效应力传递机构，而不影响P型区域中的电路元件。