公开(公告)号：US20170235866A1

公开(公告)日：2017-08-17

申请号：US15585972

申请日：2017-05-03

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Guido Ueberreiter ,  Paul Ackmann ,  Guoxiang Ning ,  Jui-Hsuan Feng ,  Chin Teong Lim

IPC: G06F17/50

CPC classification number: G06F17/5072 ,  G06F17/5081 ,  G06F2217/06 ,  G06F2217/12 ,  G06F2217/14 ,  Y02P90/265

Abstract: A method includes receiving a layout of an integrated circuit that includes a plurality of layers, one of the layers is selected and one or more tile number values are provided. A die area of the integrated circuit is partitioned into a plurality of tiles on the basis of the tile number values. It is determined, on the basis of the layout, if a portion of the selected one of the layers in the tile has an available space for inclusion of a test cell or a dummy cell, and a label indicative of a result is assigned to the tile. It is determined, on the basis of the labels assigned, if one or more space availability criteria are fulfilled and, if fulfilled, the labels are used for placing at least one of one or more test cells and one or more dummy cells in the layout.

公开(公告)号：US09672313B2

公开(公告)日：2017-06-06

申请号：US14704488

申请日：2015-05-05

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Guoxiang Ning ,  Yuping Ren ,  Chin Teong Lim ,  Xusheng Wu ,  Paul Ackmann

IPC: G06F17/50 ,  H01L23/522 ,  H01L27/02

CPC classification number: H01L23/5226 ,  G03F1/36 ,  G06F17/5077 ,  G06F17/5081 ,  G06F2217/12 ,  H01L23/528 ,  H01L23/5283 ,  H01L27/0207

Abstract: Methods for identification and partial re-routing of selected areas (e.g., including critical areas) in a layout of an IC design and the resulting device are disclosed. Embodiments include comparing design data of an IC device against criteria of manufacturing processes to manufacture the IC device; identifying in the design data a layout area based, at least in part, on proximity of metal segments, interconnecting segments, or a combination thereof in the layout area; performing partial re-routing in the layout area to substantially meet the criteria, wherein at least one interconnecting element is shifted or extended; and integrating the partial re-routing into the design data for use in the manufacturing processes.

公开(公告)号：US20160291457A1

公开(公告)日：2016-10-06

申请号：US14674157

申请日：2015-03-31

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Guido Ueberreiter ,  Guoxiang Ning ,  Jui-Hsuan Feng ,  Paul Ackmann ,  Chin Teong Lim

IPC: G03F1/36 ,  H01L21/768 ,  G03F7/30

CPC classification number: G03F1/36

Abstract: A method includes providing a pre-optical proximity correction (OPC) layout of at least a portion of at least one reticle. The pre-OPC layout defines a test cell including a first test cell area having a plurality of first target features having a first pitch and a second test cell area having a plurality of second target features having a second pitch. A post-OPC layout of the portion of the reticle is formed on the basis of the pre-OPC layout. The formation of the post-OPC layout includes performing a rule-based OPC process, wherein a plurality of first reticle features for the first test cell area are provided on the basis of the plurality of first target features, and performing a model-based OPC process, wherein a plurality of second reticle features for the second test cell area are provided on the basis of the plurality of second target features.

Abstract translation: 一种方法包括提供至少一个掩模版的至少一部分的光学前邻近校正（OPC）布局。 预OPC布局定义了包括具有多个具有第一间距的第一目标特征的第一测试单元区域和具有多个具有第二间距的第二目标特征的第二测试单元区域的测试单元。 基于OPC前的布局形成了掩模版部分的后OPC布局。 后OPC布局的形成包括执行基于规则的OPC处理，其中，基于多个第一目标特征提供用于第一测试单元区域的多个第一掩模版特征，并且执行基于模型的OPC 处理，其中，基于所述多个第二目标特征提供用于所述第二测试单元区域的多个第二掩模版特征。

公开(公告)号：US09136223B2

公开(公告)日：2015-09-15

申请号：US13952231

申请日：2013-07-26

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Guoxiang Ning ,  Soon Yoeng Tan ,  Seok Yan Poh ,  Paul Ackmann

IPC: H01L21/70 ,  H01L23/544 ,  G03F7/20 ,  G03F1/42 ,  G03F9/00

CPC classification number: H01L23/544 ,  G03F1/42 ,  G03F7/70633 ,  G03F7/70683 ,  G03F9/7076 ,  H01L21/70 ,  H01L2223/5442 ,  H01L2223/54426 ,  H01L2223/54453 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Methods for forming an alignment mark and the resulting mark are disclosed. Embodiments may include forming a first shape having rotational symmetry; forming a second shape; and forming an alignment mark by combining the first shape and one or more of the second shape, wherein the alignment mark has rotational symmetry.

Abstract translation: 公开了形成对准标记的方法和所得到的标记。 实施例可以包括形成具有旋转对称性的第一形状; 形成第二形状; 以及通过组合所述第一形状和所述第二形状中的一个或多个来形成对准标记，其中所述对准标记具有旋转对称性。

公开(公告)号：US10896874B2

公开(公告)日：2021-01-19

申请号：US16363585

申请日：2019-03-25

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Guoxiang Ning ,  Ruilong Xie ,  Lei Sun

IPC: H01L23/522 ,  H01L23/528 ,  H01L21/768 ,  H01L23/532

Abstract: Structures that include interconnects and methods of forming structures that include interconnects. A first interconnect is formed in a first trench in an interlayer dielectric layer, and a second interconnect in a second trench in the interlayer dielectric layer. The second interconnect is aligned along a longitudinal axis with the first interconnect. A dielectric region is arranged laterally arranged between the first interconnect and the second interconnect. The interlayer dielectric layer is composed of a first dielectric material, and the dielectric region is composed of a second dielectric material having a different composition than the first dielectric material.

公开(公告)号：US10892222B1

公开(公告)日：2021-01-12

申请号：US16560591

申请日：2019-09-04

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Erfeng Ding ,  Guoxiang Ning ,  Meixiong Zhao

IPC: H01L23/52 ,  H01L23/525 ,  H01L27/085 ,  H01L23/528 ,  H01L23/522

Abstract: One illustrative IC product disclosed herein includes a first conductive line positioned at a first level within the IC product and a first conductive structure positioned at a second level within the IC product, wherein the second level is lower than the first level. In this illustrative example, the IC product also includes a second conductive structure that is conductively coupled to the first conductive line, wherein at least a portion of the second conductive structure is positioned at a level that is above the first level and wherein nearest surfaces of the first conductive structure and the second conductive structure are laterally offset from one another by a lateral distance and insulating material positioned between the nearest surfaces of the first conductive structure and the second conductive structure.

公开(公告)号：US10770344B2

公开(公告)日：2020-09-08

申请号：US16244071

申请日：2019-01-09

Applicant: GLOBALFOUNDRIES INC.

Inventor： Yuping Ren ,  Haigou Huang ,  Ravi Prakash Srivastava ,  Zhiguo Sun ,  Qiang Fang ,  Cheng Xu ,  Guoxiang Ning

IPC: H01L21/768 ,  H01L23/522 ,  H01L21/311 ,  H01L21/02

Abstract: A method of fabricating interconnects in a semiconductor device is provided, which includes forming an interconnect layer having a conductive line and depositing a first aluminum-containing layer over the interconnect layer. A dielectric layer is deposited over the first aluminum-containing layer, followed by a second aluminum-containing layer deposited over the dielectric layer. A via opening is formed in the second aluminum-containing layer through to the conductive line, wherein the via opening has chamferless sidewalls.

公开(公告)号：US10727120B2

公开(公告)日：2020-07-28

申请号：US16111193

申请日：2018-08-23

Applicant: GLOBALFOUNDRIES INC.

Inventor： Sean X Lin ,  Ruilong Xie ,  Guoxiang Ning ,  Lei Sun

IPC: H01L23/48 ,  H01L21/768 ,  H01L23/522 ,  H01L23/528 ,  H01L23/58

Abstract: A method of fabricating interconnects in a semiconductor device is provided, which includes forming a metallization layer and depositing a hardmask layer over the metallization layer. A dielectric layer is deposited over the hardmask layer and an opening is formed in the dielectric layer to expose the hardmask layer. The exposed hardmask layer in the opening is etched to form an undercut beneath the dielectric layer. A metal shoulder is formed at the undercut, wherein the metal shoulder defines an aperture dimension used for forming a via opening extending to the metallization layer.

公开(公告)号：US10714422B2

公开(公告)日：2020-07-14

申请号：US16161590

申请日：2018-10-16

Applicant: GLOBALFOUNDRIES INC.

Inventor： Xiaoqiang Zhang ,  Guoxiang Ning ,  Jiehui Shu

IPC: H01L23/525 ,  H01L21/768

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to an anti-fuse with self-aligned via patterning and methods of manufacture. The anti-fuse includes: a lower wiring layer composed of a plurality of lower wiring structures; at least one via structure in direct contact and misaligned with a first wiring structure of the plurality of lower wiring structures and offset from a second wiring structure of the plurality of lower wiring structures; and an upper wiring layer composed of at least one upper wiring structure in direct contact with the at least one via structure.

公开(公告)号：US10386726B2

公开(公告)日：2019-08-20

申请号：US15720182

申请日：2017-09-29

Applicant: GLOBALFOUNDRIES INC.

Inventor： Liang Cao ,  Wenchao Jiang ,  Guoxiang Ning ,  Jie Zhang

IPC: G03F7/20 ,  G05B13/04

Abstract: Various aspects include vectorization approaches for model-based mask proximity correction (MPC). In some cases, a computer-implemented method includes: assigning a set of vectors to geometry data describing at least one mask for forming an integrated circuit (IC); adjusting a statistical predictive model of the at least one mask based upon the set of vectors and the geometry data; predicting an adjustment to the at least one mask with the statistical predictive model; and adjusting instructions for forming the at least one mask in response to a predicted mask result of the statistical predictive model deviating from a target mask result for the at least one mask.