公开(公告)号：US20150214116A1

公开(公告)日：2015-07-30

申请号：US14165107

申请日：2014-01-27

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Peter Javorka ,  Juergen Faul ,  Jan Hoentschel ,  Stefan Flachowsky ,  Ralf Richter

IPC: H01L21/8238 ,  H01L21/266 ,  H01L29/78 ,  H01L29/161 ,  H01L27/092 ,  H01L21/324 ,  H01L21/02

CPC classification number: H01L21/823807 ,  H01L21/26506 ,  H01L21/324 ,  H01L21/823814 ,  H01L27/0922 ,  H01L29/1054 ,  H01L29/165 ,  H01L29/517 ,  H01L29/6659 ,  H01L29/66636 ,  H01L29/66651 ,  H01L29/7848

Abstract: A method of forming a semiconductor device is provided including the steps of forming first and second PMOS transistor devices, wherein the first PMOS transistor devices are low, standard or high voltage threshold transistor devices and the second PMOS transistor devices are super high voltage threshold transistor devices, and wherein forming the first PMOS transistor devices includes implanting dopants to form source and drain junctions of the first PMOS transistor devices and performing a thermal anneal of the first PMOS transistor devices after implanting the dopants, and forming the second PMOS transistor devices includes implanting dopants to form source and drain junctions of the second PMOS transistor devices after performing the thermal anneal of the first PMOS transistor devices.

Abstract translation: 提供一种形成半导体器件的方法，包括以下步骤：形成第一和第二PMOS晶体管器件，其中第一PMOS晶体管器件为低标准或高电压阈值晶体管器件，而第二PMOS晶体管器件为超高电压阈值晶体管器件 并且其中形成所述第一PMOS晶体管器件包括注入掺杂剂以形成所述第一PMOS晶体管器件的源极和漏极结，并且在注入所述掺杂剂之后执行所述第一PMOS晶体管器件的热退火，以及形成所述第二PMOS晶体管器件包括注入掺杂剂 以在第一PMOS晶体管器件进行热退火之后形成第二PMOS晶体管器件的源极和漏极结。

公开(公告)号：US09082876B2

公开(公告)日：2015-07-14

申请号：US13842103

申请日：2013-03-15

Applicant: GLOBALFOUNDRIES, Inc.

Inventor： Peter Javorka ,  Ralf Richter ,  Stefan Flachowsky

IPC: H01L21/331 ,  H01L21/38 ,  H01L21/8238 ,  H01L21/266

CPC classification number: H01L21/823807 ,  H01L21/266 ,  H01L21/823814 ,  H01L21/823842 ,  H01L29/6659

Abstract: Integrated circuits and methods for fabricating integrated circuits are provided herein. In an embodiment of a method for fabricating integrated circuits, a P-type gate electrode structure and an N-type gate electrode structure are formed overlying a semiconductor substrate. The gate electrode structures each include a gate electrode that overlies a gate dielectric layer and a nitride cap that overlies the gate electrode. Conductivity determining ions are implanted into the semiconductor substrate using the P-type gate electrode structure and the N-type gate electrode structure as masks to form a source region and a drain region for the P-type gate electrode structure and the N-type gate electrode structure. The nitride cap remains overlying the N-type gate electrode structure during implantation of the conductivity determining ions into the semiconductor substrate to form the source region and the drain region for the N-type gate electrode structure.

Abstract translation: 本文提供用于制造集成电路的集成电路和方法。 在制造集成电路的方法的实施例中，在半导体衬底上形成P型栅电极结构和N型栅电极结构。 栅电极结构各自包括覆盖在栅极电介质层上的栅电极和覆盖在栅电极上的氮化物盖。 使用P型栅极电极结构和N型栅极电极结构作为掩模将电导率确定离子注入到半导体衬底中，以形成用于P型栅电极结构和N型栅极的源极区和漏极区 电极结构。 在将导电性确定离子注入半导体衬底期间，氮化物盖保持覆盖在N型栅电极结构上，以形成用于N型栅电极结构的源区和漏区。

公开(公告)号：US20150102426A1

公开(公告)日：2015-04-16

申请号：US14052977

申请日：2013-10-14

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Stefan Flachowsky ,  Jan Hoentschel ,  Ralf Richter ,  Peter Javorka

IPC: H01L29/78 ,  H01L29/66

CPC classification number: H01L29/7843 ,  H01L21/823412 ,  H01L21/823431 ,  H01L27/0886 ,  H01L29/161 ,  H01L29/66795 ,  H01L29/785

Abstract: The present invention relates to a semiconductor structure comprising at least a first and a second three-dimensional transistor, wherein the first transistor and the second transistor are electrically connected in parallel to each other, and wherein each transistor comprises a source and a drain, wherein the source and/or drain of the first transistor is at least partially separated from, respectively, the source and/or drain of the second transistor. The invention further relates to a process for realizing such a semiconductor structure.

Abstract translation: 本发明涉及包括至少第一和第二三维晶体管的半导体结构，其中第一晶体管和第二晶体管彼此并联电连接，并且其中每个晶体管包括源极和漏极，其中 第一晶体管的源极和/或漏极分别与第二晶体管的源极和/或漏极部分地分开。 本发明还涉及一种用于实现这种半导体结构的方法。

公开(公告)号：US09006835B2

公开(公告)日：2015-04-14

申请号：US14074905

申请日：2013-11-08

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Stephan Kronholz ,  Peter Javorka ,  Roman Boschke

IPC: H01L27/088 ,  H01L21/8238 ,  H01L29/78 ,  H01L29/66

CPC classification number: H01L27/088 ,  H01L21/823807 ,  H01L21/823814 ,  H01L29/665 ,  H01L29/66636 ,  H01L29/7834 ,  H01L29/7848

Abstract: A semiconductor device includes a first transistor positioned in and above a first semiconductor region, the first semiconductor region having a first upper surface and including a first semiconductor material. The semiconductor device further includes first raised drain and source portions positioned on the first upper surface of the first semiconductor region, the first drain and source portions including a second semiconductor material having a different material composition from the first semiconductor material. Additionally, the semiconductor device includes a second transistor positioned in and above a second semiconductor region, the second semiconductor region including the first semiconductor material. Finally, the semiconductor device also includes strain-inducing regions embedded in the second semiconductor region, the embedded strain-inducing regions including the second semiconductor material.

Abstract translation: 半导体器件包括位于第一半导体区域中和上方的第一晶体管，所述第一半导体区域具有第一上表面并且包括第一半导体材料。 所述半导体器件还包括位于所述第一半导体区域的所述第一上表面上的第一突起漏极和源极部分，所述第一漏极和源极部分包括具有与所述第一半导体材料不同的材料组成的第二半导体材料。 此外，半导体器件包括位于第二半导体区域中和上方的第二晶体管，第二半导体区域包括第一半导体材料。 最后，半导体器件还包括嵌入在第二半导体区域中的应变诱导区域，包括第二半导体材料的嵌入的应变诱导区域。

公开(公告)号：US20150021693A1

公开(公告)日：2015-01-22

申请号：US13943521

申请日：2013-07-16

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Peter Javorka ,  Stefan Flachowsky

IPC: H01L21/02 ,  H01L29/78

CPC classification number: H01L29/7843 ,  H01L21/0217 ,  H01L21/02211 ,  H01L21/02274 ,  H01L21/28176 ,  H01L21/3003 ,  H01L21/3115 ,  H01L21/823807 ,  H01L21/823857 ,  H01L21/823864

Abstract: When forming transistors with deuterium enhanced gate dielectrics and strained channel regions, the manufacturing processes of strain-inducing dielectric material layers formed above the transistors may be employed to efficiently introduce and diffuse the deuterium to the gate dielectrics. The incorporation of deuterium into the strain-inducing dielectric material layers may be accomplished on the basis of a deposition process in which deuterium is present in the process environment during deposition. The process temperature of the deposition process may be chosen to perform—in combination with further subsequently performed process steps—a sufficient diffusion of deuterium to the gate dielectrics.

Abstract translation: 当用氘增强的栅极电介质和应变通道区形成晶体管时，可以使用在晶体管上方形成的应变诱导电介质材料层的制造工艺来有效地将氘引入和扩散到栅极电介质。 应变诱导电介质材料层中的氘结合可以在沉积过程中基于沉积过程中完成沉积过程，其中氘存在于工艺环境中。 可以选择沉积工艺的工艺温度以与进一步随后执行的工艺步骤相结合 - 将氘充分扩散到栅极电介质。

公开(公告)号：US10340380B2

公开(公告)日：2019-07-02

申请号：US15161399

申请日：2016-05-23

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Stefan Flachowsky ,  Jan Hoentschel ,  Ralf Richter ,  Peter Javorka

IPC: H01L27/088 ,  H01L29/78 ,  H01L29/66 ,  H01L21/8234 ,  H01L29/161

Abstract: A semiconductor device includes a plurality of spaced apart fins, a dielectric material layer positioned between each of the plurality of spaced apart fins, and a common gate structure positioned above the dielectric material layer and extending across the fins. A continuous merged semiconductor material region is positioned on each of the fins and above the dielectric material layer, is laterally spaced apart from the common gate structure, extends between and physically contacts the fins, has a first sidewall surface that faces toward the common gate structure, and has a second sidewall surface that is opposite of the first sidewall surface and faces away from the common gate structure. A stress-inducing material is positioned in a space defined by at least the first sidewall surface, opposing sidewall surfaces of an adjacent pair of fins, and an upper surface of the dielectric material layer.

公开(公告)号：US20170338343A1

公开(公告)日：2017-11-23

申请号：US15161604

申请日：2016-05-23

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Sylvain Henri Baudot ,  Gunter Grasshoff ,  Juergen Faul ,  Peter Javorka

IPC: H01L29/78 ,  H01L29/06 ,  H01L27/092 ,  H01L21/8238 ,  H01L21/84 ,  H01L29/08 ,  H01L27/12

CPC classification number: H01L29/7838 ,  H01L21/76 ,  H01L21/761 ,  H01L21/76224 ,  H01L21/823814 ,  H01L21/823892 ,  H01L21/84 ,  H01L27/092 ,  H01L27/0928 ,  H01L27/1203 ,  H01L29/0649 ,  H01L29/0847 ,  H01L29/7831 ,  H01L29/78648 ,  H01L29/78654

Abstract: A semiconductor device is provided comprising a silicon-on-insulator (SOI) substrate comprising a semiconductor bulk substrate, a buried oxide layer formed on the semiconductor bulk substrate and a semiconductor layer formed on the buried oxide layer and a transistor device, wherein the transistor device comprises a gate electrode formed by a part of the semiconductor bulk substrate, a gate insulation layer formed by a part of the buried oxide layer and a channel region formed in a part of the semiconductor layer.

公开(公告)号：US20160118483A1

公开(公告)日：2016-04-28

申请号：US14522000

申请日：2014-10-23

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Stefan Flachowsky ,  Jan Hoentschel ,  Ralf Richter ,  Peter Javorka

IPC: H01L29/66 ,  H01L29/165 ,  H01L29/78

CPC classification number: H01L29/66818 ,  H01L25/0657 ,  H01L29/0634 ,  H01L29/0673 ,  H01L29/165 ,  H01L29/42376 ,  H01L29/42384 ,  H01L29/66545 ,  H01L29/785 ,  H01L29/78645 ,  H01L29/78648 ,  H01L29/78687 ,  H01L29/78696 ,  H01L2924/0002 ,  H01L2924/00

Abstract: The present disclosure provides, in various aspects of the present disclosure, a semiconductor device which includes a semiconductor stack disposed over a surface of a substrate and a gate structure partially formed over an upper surface and two opposing sidewall surfaces of the semiconductor stack, wherein the semiconductor stack includes an alternating arrangement of at least two layers formed by a first semiconductor material and a second semiconductor material which is different from the first semiconductor material.

Abstract translation: 本公开在本公开的各个方面提供一种半导体器件，其包括设置在衬底的表面上的半导体堆叠和部分地形成在半导体堆叠的上表面和两个相对的侧壁表面上的栅极结构，其中， 半导体堆叠包括由第一半导体材料和与第一半导体材料不同的第二半导体材料形成的至少两层的交替布置。

公开(公告)号：US20160064382A1

公开(公告)日：2016-03-03

申请号：US14475720

申请日：2014-09-03

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Peter Javorka ,  Stefan Flachowsky ,  Gerd Zschätzsch

IPC: H01L27/092 ,  H01L29/49 ,  H01L21/311 ,  H01L21/8238 ,  H01L21/02 ,  H01L21/308 ,  H01L29/78 ,  H01L29/66

CPC classification number: H01L27/0922 ,  H01L21/02532 ,  H01L21/28097 ,  H01L21/3083 ,  H01L21/8238 ,  H01L21/823814 ,  H01L21/823835 ,  H01L21/823842 ,  H01L27/0629 ,  H01L27/092 ,  H01L29/1608 ,  H01L29/161 ,  H01L29/165 ,  H01L29/24 ,  H01L29/267 ,  H01L29/4941 ,  H01L29/4975 ,  H01L29/517 ,  H01L29/665 ,  H01L29/66545 ,  H01L29/7848

Abstract: The present disclosure provides a method of forming a semiconductor device structure with selectively fabricating semiconductor device structures having fully silicided (FuSi) gates and partially silicided gates. In aspects of the present disclosure, a semiconductor device structure with a first semiconductor device and a second semiconductor device is provided, wherein each of the first and second semiconductor devices includes a gate structure over an active region, each of the gate structures having a gate electrode material and a gate dielectric material. The gate electrode material of the first semiconductor device is recessed, resulting in a recessed first gate electrode material which is fully silicided during a subsequent silicidation process. On the gate electrode material of the second semiconductor device, a silicide portion is formed during the silicidation process.

Abstract translation: 本公开提供了一种形成半导体器件结构的方法，其选择性地制造具有完全硅化（FuSi）栅极和部分硅化栅极的半导体器件结构。 在本公开的方面中，提供了具有第一半导体器件和第二半导体器件的半导体器件结构，其中第一和第二半导体器件中的每一个在有源区域上包括栅极结构，每个栅极结构具有栅极 电极材料和栅极电介质材料。 第一半导体器件的栅电极材料凹陷，导致凹陷的第一栅电极材料，其在随后的硅化工艺期间被完全硅化。 在第二半导体器件的栅极电极材料上，在硅化处理期间形成硅化物部分。

公开(公告)号：US09177803B2

公开(公告)日：2015-11-03

申请号：US14175288

申请日：2014-02-07

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Peter Javorka ,  Juergen Faul ,  Ralf Richter ,  Jan Hoentschel

IPC: H01L21/8234 ,  H01L21/265 ,  H01L21/28 ,  H01L21/8238 ,  H01L29/49 ,  H01L29/51 ,  H01L29/66

CPC classification number: H01L27/0883 ,  H01L21/26586 ,  H01L21/28 ,  H01L21/28255 ,  H01L21/823412 ,  H01L21/823807 ,  H01L29/1041 ,  H01L29/1054 ,  H01L29/1083 ,  H01L29/495 ,  H01L29/51 ,  H01L29/66537 ,  H01L29/6659 ,  H01L29/66651

Abstract: The present disclosure provides semiconductor device structures with a first PMOS active region and a second PMOS active region provided within a semiconductor substrate. A silicon germanium channel layer is only formed over the second PMOS active region. Gate electrodes are formed over the first and second PMOS active regions, wherein the gate electrode over the second PMOS active region is formed over the silicon germanium channel.

Abstract translation: 本公开提供半导体器件结构，其具有设置在半导体衬底内的第一PMOS有源区和第二PMOS有源区。 硅锗沟道层仅形成在第二PMOS有源区上。 栅电极形成在第一和第二PMOS有源区上，其中第二PMOS有源区上的栅电极形成在硅锗通道上。