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    Methods of forming fins for FinFET semiconductor devices and the selective removal of such fins
    31.
    发明授权
    Methods of forming fins for FinFET semiconductor devices and the selective removal of such fins 有权

    公开(公告)号：US09704973B2

    公开(公告)日：2017-07-11

    申请号：US14242130

    申请日：2014-04-01

    Applicant: GLOBALFOUNDRIES Inc.

    Inventor： Ruilong Xie ,  Andy C. Wei

    IPC: H01L29/66

    CPC classification number: H01L29/66795 ,  H01L29/66818

    Abstract: One method includes forming a plurality of first trenches in a semiconductor substrate to thereby define a plurality of initial fins in the substrate, removing at least one, but less than all, of the plurality of initial fins, forming a fin protection layer on at least the sidewalls of the remaining initial fins, with the fin protection layer in position, performing an etching process to extend a depth of the first trenches to thereby define a plurality of final trenches with a final trench depth, wherein the final trenches define a plurality of final fin structures that each comprise an initial fin, removing the fin protection layer, and forming a recessed layer of insulating material in the final trenches, wherein the recessed layer of insulating material has a recessed surface that exposes a portion of the final fin structures.

    SELF-ALIGNED VIA PROCESS FLOW
    32.
    发明申请
    SELF-ALIGNED VIA PROCESS FLOW 审中-公开
    通过过程流程自动对齐

    公开(公告)号：US20170004999A1

    公开(公告)日：2017-01-05

    申请号：US15269138

    申请日：2016-09-19

    Applicant: GLOBALFOUNDRIES Inc.

    Inventor： Guillaume Bouche ,  Andy C. Wei ,  Sudharshanan Raghunthathan

    IPC: H01L21/768 ,  H01L23/532 ,  H01L23/528 ,  H01L23/522

    CPC classification number: H01L21/76897 ,  H01L21/76802 ,  H01L21/76819 ,  H01L21/7682 ,  H01L21/76834 ,  H01L21/76835 ,  H01L21/76877 ,  H01L21/76883 ,  H01L23/5226 ,  H01L23/528 ,  H01L23/5283 ,  H01L23/5329 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: A device includes a first dielectric layer having at least one conductive feature embedded therein. A first plurality of conductive lines are embedded in a second dielectric layer disposed above the first dielectric layer. A first conductive line in the first plurality of conductive lines contacts the conductive feature and includes a conductive via portion and a recessed line portion. A second plurality of conductive lines are embedded in a third dielectric layer disposed above the second dielectric layer. A second conductive line in the second plurality of conductive lines contacts the conductive via portion and the conductive via portion has a first cross-sectional dimension corresponding to a width of the first conductive line and a second cross-sectional dimension corresponding to a width of the second conductive line.

    Abstract translation: 一种器件包括具有嵌入其中的至少一个导电特征的第一介电层。 第一多个导电线被嵌入设置在第一电介质层上方的第二电介质层中。 第一多个导电线中的第一导电线接触导电特征并且包括导电通路部分和凹陷线部分。 第二多个导电线被嵌入设置在第二电介质层上方的第三电介质层中。 第二多个导电线中的第二导线与导电通路部分接触，并且导电通路部分具有对应于第一导线的宽度的第一横截面尺寸和对应于第一导电线宽度的第二横截面尺寸 第二导线。

    Self-aligned via process flow
    34.
    发明授权
    Self-aligned via process flow 有权
    通过工艺流程自行对齐

    公开(公告)号：US09502293B2

    公开(公告)日：2016-11-22

    申请号：US14543992

    申请日：2014-11-18

    Applicant: GLOBALFOUNDRIES Inc.

    Inventor： Guillaume Bouche ,  Andy C. Wei ,  Sudharshanan Raghunthathan

    IPC: H01L21/768 ,  H01L23/522 ,  H01L23/528

    CPC classification number: H01L21/76897 ,  H01L21/76802 ,  H01L21/76819 ,  H01L21/7682 ,  H01L21/76834 ,  H01L21/76835 ,  H01L21/76877 ,  H01L21/76883 ,  H01L23/5226 ,  H01L23/528 ,  H01L23/5283 ,  H01L23/5329 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: A method includes forming a first dielectric layer having at least one conductive feature embedded therein. A first plurality of conductive lines embedded in a second dielectric layer disposed above the first dielectric layer is formed. A first conductive line in the plurality of conductive lines contacts the conductive feature. The first conductive line is etched using a first etch mask to define a conductive via portion and a recessed line portion in the first conductive line. A second plurality of conductive lines embedded in a third dielectric layer disposed above the second dielectric layer is formed. A second conductive line in the second plurality of conductive lines contacts the conductive via portion and the third dielectric layer directly contacts the second dielectric layer.

    Abstract translation: 一种方法包括形成具有嵌入其中的至少一个导电特征的第一电介质层。 形成嵌入在设置在第一电介质层上方的第二电介质层中的第一多个导电线。 多个导线中的第一导线接触导电特征。 使用第一蚀刻掩模蚀刻第一导电线以在第一导电线中限定导电通路部分和凹陷线部分。 形成嵌入在第二电介质层上方的第三电介质层中的第二多个导电线。 第二多个导电线中的第二导线接触导电通路部分，第三电介质层直接接触第二电介质层。

    METHODS OF FORMING NANOWIRE DEVICES WITH SPACERS AND THE RESULTING DEVICES
    37.
    发明申请
    METHODS OF FORMING NANOWIRE DEVICES WITH SPACERS AND THE RESULTING DEVICES 有权
    形成具有间隔器和结果器件的纳米器件的方法

    公开(公告)号：US20150372111A1

    公开(公告)日：2015-12-24

    申请号：US14308257

    申请日：2014-06-18

    Applicant: GLOBALFOUNDRIES Inc.

    Inventor： Shao-Ming Koh ,  Guillaume Bouche ,  Jing Wan ,  Andy C. Wei

    IPC: H01L29/66 ,  H01L29/76

    CPC classification number: H01L29/66439 ,  B82Y10/00 ,  B82Y40/00 ,  H01L29/0673 ,  H01L29/1054 ,  H01L29/66492 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/66575 ,  H01L29/6659 ,  H01L29/66636 ,  H01L29/775

    Abstract: A method of forming a nanowire device includes forming semiconductor material layers above a semiconductor substrate, forming a gate structure above the semiconductor material layers, forming a first sidewall spacer adjacent to the gate structure and forming a second sidewall spacer adjacent to the first sidewall spacer. The method further includes patterning the semiconductor material layers such that each layer has first and second exposed end surfaces. The gate structure, the first sidewall spacer, and the second sidewall spacer are used in combination as an etch mask during the patterning process. The method further includes removing the first and second sidewall spacers, thereby exposing at least a portion of the patterned semiconductor material layers. The method further includes forming doped extension regions in at least the exposed portions of the patterned semiconductor material layers after removing the first and second sidewall spacers.

    Abstract translation: 形成纳米线器件的方法包括在半导体衬底之上形成半导体材料层，在半导体材料层之上形成栅极结构，形成与栅极结构相邻的第一侧壁间隔物，并形成邻近第一侧壁间隔物的第二侧壁间隔物。 该方法还包括使半导体材料层图案化，使得每个层具有第一和第二暴露的端表面。 栅极结构，第一侧壁间隔件和第二侧壁间隔件在图案化工艺期间被组合用作蚀刻掩模。 该方法还包括去除第一和第二侧壁间隔物，从而暴露图案化的半导体材料层的至少一部分。 该方法还包括在除去第一和第二侧壁间隔物之后，在至少图案化的半导体材料层的暴露部分中形成掺杂的延伸区域。

    Integrated circuits with metal-insulator-semiconductor (MIS) contact structures and methods for fabricating same
    38.
    发明授权
    Integrated circuits with metal-insulator-semiconductor (MIS) contact structures and methods for fabricating same 有权
    具有金属绝缘体半导体（MIS）接触结构的集成电路及其制造方法

    公开(公告)号：US09177805B2

    公开(公告)日：2015-11-03

    申请号：US14166660

    申请日：2014-01-28

    Applicant: GLOBALFOUNDRIES, Inc.

    Inventor： Guillaume Bouche ,  Shao Ming Koh ,  Jeremy A. Wahl ,  Andy C. Wei

    IPC: H01L21/00 ,  H01L21/84 ,  H01L21/28 ,  H01L21/8238 ,  H01L27/092

    CPC classification number: H01L21/2807 ,  H01L21/28158 ,  H01L21/823821 ,  H01L21/845 ,  H01L27/0924 ,  H01L27/1211 ,  H01L29/41791 ,  H01L29/66545 ,  H01L29/66795

    Abstract: Integrated circuits having metal-insulator-semiconductor (MIS) contact structures and methods for fabricating integrated circuits having metal-insulator-semiconductor (MIS) contact structures are provided. In an embodiment, a method for fabricating an integrated circuit includes providing a fin structure formed from semiconductor material overlying a semiconductor substrate. The method includes depositing a layer of high-k dielectric material over the fin structure. Further, the method includes forming a metal layer or layers over the layer of high-k dielectric material to provide the fin structure with a metal-insulator-semiconductor (MIS) contact structure.

    Abstract translation: 提供了具有金属 - 绝缘体半导体（MIS）接触结构的集成电路以及用于制造具有金属 - 绝缘体 - 半导体（MIS））接触结构的集成电路的方法。 在一个实施例中，制造集成电路的方法包括提供由半导体材料覆盖在半导体衬底上形成的鳍结构。 该方法包括在鳍结构上沉积高k电介质材料层。 此外，该方法包括在高k电介质材料层上形成金属层，以使鳍结构具有金属 - 绝缘体半导体（MIS）接触结构。

    METHODS OF FORMING CONTACTS TO SOURCE/DRAIN REGIONS OF FINFET DEVICES BY FORMING A REGION THAT INCLUDES A SCHOTTKY BARRIER LOWERING MATERIAL
    40.
    发明申请
    METHODS OF FORMING CONTACTS TO SOURCE/DRAIN REGIONS OF FINFET DEVICES BY FORMING A REGION THAT INCLUDES A SCHOTTKY BARRIER LOWERING MATERIAL 审中-公开
    通过形成包含肖特基阻挡层材料的区域形成FINFET器件的源/漏区域的方法

    公开(公告)号：US20140273365A1

    公开(公告)日：2014-09-18

    申请号：US13798503

    申请日：2013-03-13

    Applicant: GLOBALFOUNDRIES Inc.

    Inventor： Andy C. Wei ,  Shao Ming Koh

    IPC: H01L21/8238 ,  H01L29/66

    CPC classification number: H01L21/823821 ,  H01L21/845 ,  H01L29/66545 ,  H01L29/66795

    Abstract: Various methods of forming conductive contacts to the source/drain regions of FinFET devices that involves forming a region comprised of a Schottkky barrier lowering material are disclosed. The method disclosed herein includes forming at least one fin for an N-type FinFET device (or a P-type FinFET device) in a semiconducting substrate, performing at least one process operation to form a region in the at least one fin that contains a Schottky barrier lowering material, depositing a layer of a valence band metal (for an N-type device) or a conduction band metal (for a P-type device) on the region and forming a metal silicide region on the fin, wherein the metal silicide is comprised of the valance band metal (for the N-type device) or a conduction band metal (for the P-type device).

    Abstract translation: 公开了向包括形成由肖特基势垒降低材料构成的区域的FinFET器件的源极/漏极区域形成导电触点的各种方法。 本文公开的方法包括在半导体衬底中形成用于N型FinFET器件（或P型FinFET器件）的至少一个鳍片，执行至少一个工艺操作以在至少一个鳍片中形成包含 肖特基势垒降低材料，在该区域上沉积价带金属层（用于N型器件）或导带金属（用于P型器件），并在鳍片上形成金属硅化物区域，其中金属 硅化物由价带金属（用于N型器件）或导带金属（用于P型器件）组成。

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