公开(公告)号：US20160049427A1

公开(公告)日：2016-02-18

申请号：US14461700

申请日：2014-08-18

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Hui ZANG

IPC: H01L27/12 ,  H01L21/84 ,  H01L29/66 ,  H01L21/3105 ,  H01L21/321 ,  H01L21/768 ,  H01L23/528 ,  H01L21/311

CPC classification number: H01L27/1211 ,  H01L21/31053 ,  H01L21/31111 ,  H01L21/32115 ,  H01L21/76829 ,  H01L21/76897 ,  H01L21/845 ,  H01L23/528 ,  H01L29/41783 ,  H01L29/41791 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/785 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Devices and methods for forming semiconductor devices with self aligned contacts for improved process windows are provided. One method includes, for instance: obtaining a wafer with at least two gates, forming partial spacers adjacent to the at least two gates, and forming at least one contact on the wafer. One intermediate semiconductor device includes, for instance: a wafer with an isolation region, at least two gates disposed on the isolation region, at least one source region disposed on the isolation region, at least one drain region disposed on the isolation region, and at least one contact positioned between the at least two gates, wherein a first portion of the at least one contact engages the at least one source region or the at least one drain region and a second portion of the at least one contact extends above a top surface of the at least two gates.

公开(公告)号：US20150194517A1

公开(公告)日：2015-07-09

申请号：US14147181

申请日：2014-01-03

Applicant: GLOBALFOUNDRIES INC.

Inventor： Hui ZANG

IPC: H01L29/78 ,  H01L21/02 ,  H01L21/283 ,  H01L29/66

CPC classification number: H01L29/7851 ,  H01L21/02057 ,  H01L21/02112 ,  H01L21/283 ,  H01L21/76834 ,  H01L21/76897 ,  H01L21/823418 ,  H01L29/0653 ,  H01L29/41775 ,  H01L29/41791 ,  H01L29/4238 ,  H01L29/45 ,  H01L29/4966 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/785

Abstract: A process for fabrication of semiconductor devices, particularly FinFETs, having a low contact horizontal resistance and a resulting device are provided. Embodiments include: providing a substrate having source and drain regions separated by a gate region; forming a gate electrode having a first length on the gate region; forming an epitaxy layer on the source and drain regions; forming a contact layer having a second length, longer than the first length, at least partially on the epitaxy layer; and forming an oxide layer on top and side surfaces of the contact layer for at least the first length.

Abstract translation: 提供了具有低接触水平电阻的半导体器件，特别是FinFET的制造工艺和所得到的器件。 实施例包括：提供具有由栅极区域分隔的源极和漏极区域的衬底; 在所述栅极区上形成具有第一长度的栅电极; 在源极和漏极区上形成外延层; 在所述外延层上至少部分地形成具有比所述第一长度长的第二长度的接触层; 以及在所述接触层的顶表面和侧表面上形成至少第一长度的氧化物层。

公开(公告)号：US20200335619A1

公开(公告)日：2020-10-22

申请号：US16386902

申请日：2019-04-17

Applicant: GLOBALFOUNDRIES INC.

Inventor： Yanping SHEN ,  Haiting WANG ,  Hui ZANG ,  Jiehui SHU

IPC: H01L29/78 ,  H01L21/8238 ,  H01L21/8234 ,  H01L29/66

Abstract: The present disclosure generally relates to semiconductor structures and, more particularly, to middle of line gate structures and methods of manufacture. The structure includes: a plurality of adjacent gate structures; a bridged gate structure composed of a plurality of the adjacent gate structures; source and drain regions adjacent to the bridged gate structure and comprising source and drain metallization features; and contacts to the bridged gate structure and the source and drain metallization features.

公开(公告)号：US20190305105A1

公开(公告)日：2019-10-03

申请号：US15943272

申请日：2018-04-02

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Qun GAO ,  Christopher NASSAR ,  Sugirtha KRISHNAMURTHY ,  Domingo Antonio FERRER LUPPI ,  John SPORRE ,  Shahab SIDDIQUI ,  Beth BAUMERT ,  Abu ZAINUDDIN ,  Jinping LIU ,  Tae Jeong LEE ,  Luigi PANTISANO ,  Heather LAZAR ,  Hui ZANG

IPC: H01L29/66 ,  H01L29/78 ,  H01L29/49 ,  H01L29/423

Abstract: A method for controlling the gate length within a FinFET device to increase power performance and the resulting device are provided. Embodiments include forming a vertical gate to extend over a plurality of fins; depositing a respective oxide layer over each of a plurality of skirt regions formed at respective points of intersection of the vertical gate with the plurality of fins; and oxidizing each oxide layer to form a plurality of oxidized gate skirts.

公开(公告)号：US20190259667A1

公开(公告)日：2019-08-22

申请号：US15898569

申请日：2018-02-17

Applicant: GLOBALFOUNDRIES INC.

Inventor： Hui ZANG ,  Ruilong XIE

IPC: H01L21/8234 ,  H01L27/088 ,  H01L29/66 ,  H01L29/08

Abstract: The present disclosure generally relates to semiconductor structures and, more particularly, to middle of line structures and methods of manufacture. The structure includes: a plurality of gate structures comprising source and drain regions; contacts connecting to the source and drain regions; contacts connecting to the gate structures which are offset from the contacts connecting to the source and drain regions; and interconnect structures in electrical contact with the contacts of the gate structures and the contacts of the source and drain regions.

公开(公告)号：US20190229183A1

公开(公告)日：2019-07-25

申请号：US15875132

申请日：2018-01-19

Applicant: GLOBALFOUNDRIES INC.

Inventor： Haiting WANG ,  Hui ZANG ,  Chun Yu WONG ,  Kwan-Yong LIM

IPC: H01L29/06 ,  H01L27/088 ,  H01L21/762

Abstract: A methodology for forming a single diffusion break structure in a FinFET device involves localized, in situ oxidation of a portion of a semiconductor fin. Fin oxidation within a fin cut region may be preceded by the formation of epitaxial source/drain regions over the fin, as well as by a gate cut module, where portions of a sacrificial gate that straddle the fin are replaced by an isolation layer. Localized oxidation of the fin enables the stress state in adjacent, un-oxidized portions of the fin to be retained, which may beneficially impact carrier mobility and hence conductivity within channel portions of the fin.

公开(公告)号：US20190067474A1

公开(公告)日：2019-02-28

申请号：US15686257

申请日：2017-08-25

Applicant: GLOBALFOUNDRIES INC.

Inventor： Chun Yu WONG ,  Hui ZANG

IPC: H01L29/78 ,  H01L29/66 ,  H01L29/08 ,  H01L21/02 ,  H01L21/265 ,  H01L29/165 ,  H01L29/10

Abstract: A polysilicon layer is deposited over the top surface of the source/drain region of a semiconductor fin in a vertical fin field effect transistor and recrystallized prior to the formation of an epitaxial source/drain region over the source/drain region. The recrystallized silicon material increases the area for deposition of the source/drain region, increasing the available contact area of the source/drain region and correspondingly decreasing the contact resistance thereto. Prior to recrystallization, the polysilicon layer may be made amorphous to improve the quality of the crystalline material for epitaxial growth.

公开(公告)号：US20180330994A1

公开(公告)日：2018-11-15

申请号：US15590195

申请日：2017-05-09

Applicant: GLOBALFOUNDRIES INC.

Inventor： Hui ZANG ,  Jinping LIU

IPC: H01L21/8234 ,  H01L29/417

CPC classification number: H01L21/823431 ,  H01L21/0217 ,  H01L21/02348 ,  H01L27/0886 ,  H01L29/41791

Abstract: A multi-masking process is used to form semiconductor fin arrays having a controlled and variable fin pitch and fin critical dimension within different arrays. A layer of curable silicon nitride is incorporated into a patterning architecture, patterned to form an etch mask, and locally cured to further modify the etch mask geometry. The use of cured and uncured structures facilitate the tuning of the resultant fin geometry.

公开(公告)号：US20180138177A1

公开(公告)日：2018-05-17

申请号：US15352963

申请日：2016-11-16

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Tek Po Rinus LEE ,  Bharat KRISHNAN ,  Jinping LIU ,  Hui ZANG ,  Judson Robert HOLT

IPC: H01L27/092 ,  H01L21/8238 ,  H01L21/02 ,  H01L21/3205 ,  H01L29/08 ,  H01L29/45 ,  H01L29/66

CPC classification number: H01L27/092 ,  H01L21/28525 ,  H01L21/76843 ,  H01L21/76858 ,  H01L21/76865 ,  H01L21/823814 ,  H01L21/823871 ,  H01L23/485 ,  H01L29/165 ,  H01L29/41783 ,  H01L29/45 ,  H01L29/456

Abstract: Formation of band-edge contacts include, for example, providing an intermediate semiconductor structure comprising a substrate and a gate thereon and source/drain regions adjacent the gate, depositing a non-epitaxial layer on the source/drain regions, deposing a metal layer on the non-epitaxial layer, and forming metal alloy contacts from the deposited non-epitaxial layer and metal layer on the source/drain regions by annealing the deposited non-epitaxial layer and metal layer.

公开(公告)号：US20180097089A1

公开(公告)日：2018-04-05

申请号：US15821091

申请日：2017-11-22

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Hui ZANG ,  Bingwu LIU

IPC: H01L29/66 ,  H01L29/78

CPC classification number: H01L29/66795 ,  H01L29/66545 ,  H01L29/7848 ,  H01L29/785

Abstract: Devices and methods of growing unmerged epitaxy for fin field-effect transistor (FinFet) devices are provided. One method includes, for instance: obtaining a wafer having at least one source, at least one drain, and at least one fin; etching to expose at least a portion of the at least one fin; forming at least one sacrificial gate structure; and forming a first layer of an epitaxial growth on the at least one fin. One device includes, for instance: a wafer having at least one source, at least one drain, and at least one fin; a first layer of an epitaxial growth on the at least one fin; at least one second layer of an epitaxial growth superimposing the first layer of an epitaxial growth; and a first contact region over the at least one source and a second contact region over the at least one drain.