公开(公告)号：US09496341B1

公开(公告)日：2016-11-15

申请号：US14730320

申请日：2015-06-04

Applicant: GLOBALFOUNDRIES INC.

Inventor： Kangguo Cheng ,  Judson Holt ,  Shogo Mochizuki

IPC: H01L29/47 ,  H01L29/10 ,  H01L29/78 ,  H01L29/16 ,  H01L29/161 ,  H01L21/02 ,  H01L21/306 ,  H01L21/324 ,  H01L21/762 ,  H01L29/06

CPC classification number: H01L29/1054 ,  H01L21/02447 ,  H01L21/0245 ,  H01L21/02529 ,  H01L21/02532 ,  H01L21/02664 ,  H01L21/18 ,  H01L21/7624 ,  H01L29/161 ,  H01L29/785

Abstract: A method includes forming a multilayered stack on a surface of a supporting layer. The multilayered stack is composed of alternating layers of compressively strained Silicon Germanium (Si1-xGex) and tensily strained Carbon-doped Silicon (Si:C). The method further includes etching the multilayered stack to form at least one Fin precursor structure and annealing the Fin precursor structure to remove Carbon from the strained Si:C layers to form Carbon-depleted layers and to diffuse Germanium from the Si1-xGex layers into the Carbon-depleted layers producing a Si1-xGex Fin. A structure that is disclosed includes a Semiconductor on Insulator (SOI) layer disposed on a layer of buried oxide and a multilayered stack on a surface of the SOI layer. The multilayered stack is composed of alternating layers of compressively strained Si1-xGex and tensily strained Si:C. The structure further includes a hardmask layer disposed on a top surface of the multilayered stack.

Abstract translation: 一种方法包括在支撑层的表面上形成多层叠层。 多层堆叠由压缩应变硅锗（Si1-xGex）和紧张应变碳掺杂硅（Si：C）的交替层组成。 该方法还包括蚀刻多层堆叠以形成至少一个Fin前体结构并退火Fin前体结构以从应变的Si：C层去除碳以形成贫碳层并将锗从Si1-xGex层扩散到 生产Si1-xGex Fin的碳耗尽层。 所公开的结构包括在SOI层的表面上设置在掩埋氧化物层和多层叠层上的半导体绝缘体（SOI）层。 多层堆叠由压缩应变Si1-xGex和紧张应变Si：C的交替层组成。 该结构还包括设置在多层堆叠的顶表面上的硬掩模层。

公开(公告)号：US09484359B2

公开(公告)日：2016-11-01

申请号：US14696736

申请日：2015-04-27

Applicant: GLOBALFOUNDRIES INC.

Inventor： Kangguo Cheng ,  Bruce B Doris ,  Pranita Kerber ,  Ali Khakifirooz

IPC: H01L27/12 ,  H01L21/84 ,  H01L21/265 ,  H01L29/66 ,  H01L29/786 ,  H01L21/762 ,  H01L29/45 ,  H01L29/78

CPC classification number: H01L27/1203 ,  H01L21/2652 ,  H01L21/26586 ,  H01L21/76267 ,  H01L21/84 ,  H01L29/45 ,  H01L29/66772 ,  H01L29/7831 ,  H01L29/78648

Abstract: An SOI substrate, a semiconductor device, and a method of backgate work function tuning. The substrate and the device have a plurality of metal backgate regions wherein at least two regions have different work functions. The method includes forming a mask on a substrate and implanting a metal backgate interposed between a buried oxide and bulk regions of the substrate thereby producing at least two metal backgate regions having different doses of impurity and different work functions. The work function regions can be aligned such that each transistor has different threshold voltage. When a top gate electrode serves as the mask, a metal backgate with a first work function under the channel region and a second work function under the source/drain regions is formed. The implant can be tilted to shift the work function regions relative to the mask.

公开(公告)号：US09478600B2

公开(公告)日：2016-10-25

申请号：US14175587

申请日：2014-02-07

Applicant: GLOBALFOUNDRIES INC.

Inventor： Geng Wang ,  Roger A. Booth, Jr. ,  Kangguo Cheng ,  Joseph Ervin ,  Chengwen Pei ,  Ravi M. Todi

IPC: H01L49/02 ,  H01L21/762 ,  H01L21/74 ,  H01L21/84 ,  H01L27/108 ,  H01L27/12 ,  H01L29/66 ,  H01L29/06 ,  H01L21/02

CPC classification number: H01L28/40 ,  H01L21/02529 ,  H01L21/02532 ,  H01L21/0262 ,  H01L21/743 ,  H01L21/76224 ,  H01L21/76229 ,  H01L21/84 ,  H01L27/1087 ,  H01L27/1203 ,  H01L28/91 ,  H01L29/0649 ,  H01L29/66181

Abstract: A semiconductor structure is provided that includes a material stack including an epitaxially grown semiconductor layer on a base semiconductor layer, a dielectric layer on the epitaxially grown semiconductor layer, and an upper semiconductor layer present on the dielectric layer. A capacitor is present extending from the upper semiconductor layer through the dielectric layer into contact with the epitaxially grown semiconductor layer. The capacitor includes a node dielectric present on the sidewalls of the trench and an upper electrode filling at least a portion of the trench. A substrate contact is present in a contact trench extending from the upper semiconductor layer through the dielectric layer and the epitaxially semiconductor layer to a doped region of the base semiconductor layer. A substrate contact is also provided that contacts the base semiconductor layer through the sidewall of a trench. Methods for forming the above-described structures are also provided.

公开(公告)号：US09472446B2

公开(公告)日：2016-10-18

申请号：US14307902

申请日：2014-06-18

Applicant: GLOBALFOUNDRIES Inc. ,  International Business Machines Corporation

Inventor： Ruilong Xie ,  Xiuyu Cai ,  Kangguo Cheng ,  Ali Khakifirooz

IPC: H01L21/336 ,  H01L21/762 ,  H01L29/78 ,  H01L29/66 ,  H01L29/51 ,  H01L29/10 ,  H01L21/306 ,  H01L21/3065 ,  H01L21/308 ,  H01L21/84 ,  H01L21/8238 ,  H01L21/8234

CPC classification number: H01L21/76224 ,  H01L21/30608 ,  H01L21/3065 ,  H01L21/3083 ,  H01L21/823431 ,  H01L21/823821 ,  H01L21/845 ,  H01L29/1029 ,  H01L29/51 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/66818 ,  H01L29/785 ,  H01L29/7853

Abstract: One method disclosed includes, among other things, forming an overall fin structure having a stepped cross-sectional profile, the fin structure having an upper part and a lower part positioned under the upper part, wherein the upper part has a first width and the lower part has a second width that is less than the first width, forming a layer of insulating material in trenches adjacent the overall fin structure such that the upper part of the overall fin structure and a portion of the lower part of the overall fin structure are exposed above an upper surface of the layer of insulating material, and forming a gate structure around the exposed upper part of the overall fin structure and the exposed portion of the lower part of the overall fin structure.

Abstract translation: 所公开的一种方法包括形成具有阶梯状横截面轮廓的整体翅片结构，翅片结构具有位于上部下方的上部和下部，其中上部具有第一宽度和下部 部分具有小于第一宽度的第二宽度，在邻近整个翅片结构的沟槽中形成绝缘材料层，使得整个翅片结构的上部和整个翅片结构的下部的一部分暴露 在绝缘材料层的上表面之上，并且围绕整个翅片结构的暴露的上部和整个翅片结构的下部的暴露部分形成栅极结构。

公开(公告)号：US09455331B1

公开(公告)日：2016-09-27

申请号：US14796646

申请日：2015-07-10

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION ,  GLOBALFOUNDRIES INC.

Inventor： Xiuyu Cai ,  Kangguo Cheng ,  Ali Khakifirooz ,  Ruilong Xie ,  Tenko Yamashita

IPC: H01L21/8236 ,  H01L29/66 ,  H01L29/78 ,  H01L29/417 ,  H01L29/06

CPC classification number: H01L27/0886 ,  H01L27/0207 ,  H01L29/0649 ,  H01L29/41791 ,  H01L29/6656 ,  H01L29/66795 ,  H01L29/6681 ,  H01L29/7848 ,  H01L29/785

Abstract: A method of forming a semiconductor device that includes forming a plurality of semiconductor pillars. A dielectric spacer is formed between at least one set of adjacent semiconductor pillars. Semiconductor material is epitaxially formed on sidewalls of the adjacent semiconductor pillars, wherein the dielectric spacer obstructs a first portion of epitaxial semiconductor material formed on a first semiconductor pillar from merging with a second portion of epitaxial semiconductor material formed on a second semiconductor pillar.

Abstract translation: 一种形成包括形成多个半导体柱的半导体器件的方法。 在至少一组相邻的半导体柱之间形成介电间隔物。 半导体材料外延地形成在相邻半导体柱的侧壁上，其中电介质间隔物阻挡形成在第一半导体柱上的外延半导体材料的第一部分与形成在第二半导体柱上的第二部分外延半导体材料合并。

公开(公告)号：US09418902B2

公开(公告)日：2016-08-16

申请号：US14050661

申请日：2013-10-10

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Kangguo Cheng ,  Shom S. Ponoth ,  Balasubramanian Pranatharthiharan ,  Theodorus E. Standaert ,  Tenko Yamashita

IPC: H01L21/84 ,  H01L21/762 ,  H01L27/12 ,  H01L29/66

CPC classification number: H01L21/845 ,  H01L21/32 ,  H01L21/76243 ,  H01L27/1211 ,  H01L29/66545 ,  H01L29/66795

Abstract: A method of isolating a semiconductor fin from an underlying substrate including forming a masking layer around a base portion of the fin, forming spacers on a top portion of the fin above the masking layer, removing the masking layer to expose the base portion of the fin, and converting the base portion of the fin to an isolation region that electrically isolates the fin from the substrate. The base portion of the fin may be converted to an isolation region by oxidizing the base portion of the fin, using for example a thermal oxidation process. While converting the base portion of the fin to an isolation region, the spacers prevent the top portion of the fin from also being converted.

Abstract translation: 一种从下面的衬底隔离半导体鳍片的方法，包括在鳍片的基底部分周围形成掩模层，在掩模层上方的翅片的顶部上形成间隔物，去除掩模层以暴露鳍片的基底部分 ，并且将鳍的基部转换成将鳍与基板电隔离的隔离区。 通过使用例如热氧化工艺，可以通过氧化散热片的基部来将散热片的基部转换成隔离区。 在将翅片的基部转换成隔离区域的同时，间隔物防止鳍的顶部也被转换。

公开(公告)号：US09389319B2

公开(公告)日：2016-07-12

申请号：US14699557

申请日：2015-04-29

Applicant: GLOBALFOUNDRIES INC.

Inventor： Qing Cao ,  Kangguo Cheng ,  Zhengwen Li ,  Fei Liu ,  Zhen Zhang

IPC: G01T1/04 ,  G01T1/06

CPC classification number: G01T1/06

Abstract: A method for colorimetric radiation dosimetry includes subjecting an aggregate including a polymeric matrix having uniformly dispersed nanoparticles therein to radiation. The aggregate is soaked in a solution selected to dissolve decomposed pieces of the polymeric matrix to release into the solution nanoparticles from the decomposed pieces. Color of the solution is compared to a reference to determine a dose of radiation based on number of liberated nanoparticles.

公开(公告)号：US09385023B1

公开(公告)日：2016-07-05

申请号：US14712462

申请日：2015-05-14

Applicant: GLOBALFOUNDRIES INC.

Inventor： Kangguo Cheng ,  Joel P. de Souza ,  Ali Khakifirooz ,  Alexander Reznicek ,  Dominic J. Schepis

IPC: H01L21/84 ,  H01L21/336 ,  H01L21/76 ,  H01L27/12 ,  H01L21/70 ,  H01L21/762 ,  H01L21/225 ,  H01L21/283 ,  H01L29/66 ,  H01L29/78 ,  H01L29/06

CPC classification number: H01L21/76243 ,  H01L21/2253 ,  H01L21/283 ,  H01L21/306 ,  H01L21/3063 ,  H01L21/76245 ,  H01L21/845 ,  H01L27/1211 ,  H01L29/0657 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/785 ,  H01L29/7855

Abstract: A semiconductor structure is provided that contains silicon fins having different heights, while maintaining a reasonable fin height to width ratio for process feasibility. The semiconductor structure includes a first silicon fin of a first height that is located on a first buried oxide structure. The structure further includes a second silicon fin of a second height that is located on a second buried oxide structure that is spaced apart from the first buried oxide structure. The second height of the second silicon fin is greater than the first height of the first silicon fin, yet a topmost surface of the first silicon fin is coplanar of a topmost surface with the second silicon fin.

Abstract translation: 提供了包含具有不同高度的硅散热片的半导体结构，同时为了工艺可行性而保持合理的翅片高宽比。 半导体结构包括位于第一掩埋氧化物结构上的第一高度的第一硅鳍。 该结构还包括第二高度的第二硅片，其位于与第一掩埋氧化物结构间隔开的第二掩埋氧化物结构上。 第二硅片的第二高度大于第一硅片的第一高度，但是第一硅片的最顶面与第二硅片的最顶面共面。

公开(公告)号：US09379135B2

公开(公告)日：2016-06-28

申请号：US14723681

申请日：2015-05-28

Applicant: GLOBALFOUNDRIES INC.

Inventor： Kangguo Cheng ,  Ali Khakifirooz ,  Shom Ponoth ,  Raghavasimhan Sreenivasan

IPC: H01L27/12 ,  H01L21/762 ,  H01L21/84 ,  H01L29/66 ,  H01L29/06 ,  H01L29/423 ,  H01L29/78

CPC classification number: H01L27/1211 ,  H01L21/76205 ,  H01L21/845 ,  H01L29/0649 ,  H01L29/4238 ,  H01L29/6681 ,  H01L29/785

Abstract: A semiconductor device includes a silicon-on-insulator (SOI) substrate having a buried oxide (BOX) layer, and a plurality of semiconductor fins formed on the BOX layer. The plurality of semiconductor fins include at least one pair of fins defining a BOX region therebetween. Gate lines are formed on the SOI substrate and extend across the plurality of semiconductor fins. Each gate line initially includes a dummy gate and a hardmask. A high dielectric (high-k) layer is formed on the hardmask and the BOX regions. At least one spacer is formed on each gate line such that the high-k layer is disposed between the spacer and the hardmask. A replacement gate process replaces the hardmask and the dummy gate with a metal gate. The high-k layer is ultimately removed from the gate line, while the high-k layer remains on the BOX region.

公开(公告)号：US20160172314A1

公开(公告)日：2016-06-16

申请号：US14566773

申请日：2014-12-11

Applicant: GLOBALFOUNDRIES INC.

Inventor： Kangguo Cheng ,  Joseph Ervin ,  Juntao Li ,  Chengwen Pei ,  Geng Wang

IPC: H01L23/00 ,  H01L21/762 ,  H01L29/06

CPC classification number: H01L23/564 ,  H01L21/26586 ,  H01L21/743 ,  H01L21/76229 ,  H01L21/84 ,  H01L29/0646 ,  H01L29/0649 ,  H01L29/66181 ,  H01L29/945 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A semiconductor structure is provided that includes a semiconductor on insulator (SOI) substrate comprising a bottom semiconductor layer, an epitaxial semiconductor layer present on the bottom semiconductor layer, a buried insulator layer present on the epitaxial semiconductor layer, and a top semiconductor layer present on the buried insulator layer. A deep trench moat (DTMOAT) is disposed in the SOI substrate and has a bottom surface contacting a dopant region of the bottom semiconductor layer. A moat contact electrically connecting the DTMOAT to the epitaxial semiconductor layer of the SOI substrate. Charges accumulated in the DTMOAT can be discharged through the heavily doped epitaxial semiconductor layer to ground, thus preventing the DTMOAT failure caused by the process-induced charge accumulation.

Abstract translation: 提供一种半导体结构，其包括半导体绝缘体（SOI）衬底，其包括底部半导体层，存在于底部半导体层上的外延半导体层，存在于外延半导体层上的掩埋绝缘体层以及存在于外部半导体层上的顶部半导体层 埋层绝缘体层。 深沟槽沟（DTMOAT）设置在SOI衬底中并具有与底部半导体层的掺杂区接触的底面。 将DTMOAT电连接到SOI衬底的外延半导体层的护套接点。 在DTMOAT中累积的电荷可以通过重掺杂的外延半导体层放电到地面，从而防止由过程引起的电荷积累引起的DTMOAT故障。