公开(公告)号：US09978608B2

公开(公告)日：2018-05-22

申请号：US15271511

申请日：2016-09-21

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Ruilong Xie ,  Min Gyu Sung ,  Nigel G. Cave ,  Lars Liebmann

IPC: H01L21/70 ,  H01L21/308 ,  H01L29/10 ,  H01L29/78 ,  H01L29/66 ,  H01L21/3065

CPC classification number: H01L21/3088 ,  H01L21/3065 ,  H01L21/3081 ,  H01L21/3085 ,  H01L21/3086 ,  H01L29/1037 ,  H01L29/66795 ,  H01L29/7851

Abstract: Methods for fabricating fins for a fin-type field-effect transistor (FinFET) and fin structures for a FinFET. A conformal layer is formed that includes respective first portions on sidewalls of first hardmask sections previously formed on a substrate, a recess between the first portions on the sidewalls of each adjacent pair of the first hardmask sections, and a second portion between the substrate and the recess. The conformal layer is constituted by a second material chosen to etch selectively to the first material constituting the first hardmask sections. A spacer is formed in each recess and masks the respective second portion of the conformal layer. The conformal layer is then etched to form second hardmask sections each comprised of one of the second portions of the conformal layer. The substrate is etched with the first and second hardmask sections masking the substrate to form a plurality of fins.

公开(公告)号：US20180096932A1

公开(公告)日：2018-04-05

申请号：US15285092

申请日：2016-10-04

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Ruilong Xie ,  Lars Liebmann ,  Daniel Chanemougame ,  Geng Han

IPC: H01L23/528 ,  H01L21/768 ,  H01L21/02 ,  H01L29/40 ,  H01L23/522

CPC classification number: H01L21/76816 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/76802 ,  H01L21/76814 ,  H01L21/76832 ,  H01L21/76835 ,  H01L21/76861 ,  H01L21/76877 ,  H01L21/76879 ,  H01L23/5226 ,  H01L23/5283 ,  H01L29/401

Abstract: One illustrative method disclosed includes, among other things, forming a layer of insulating material comprising a first insulating material above a substrate and forming a metallization blocking structure in the layer of insulating material at a location that is in a path of a metallization trench to be formed in the layer of insulating material, the metallization blocking structure comprising a second insulating material that is different from the first insulating material. The method also includes forming the metallization trench in the layer of insulating material on opposite sides of the metallization blocking structure and forming a conductive metallization line in the metallization trench on opposite sides of the metallization blocking structure.

公开(公告)号：US09929048B1

公开(公告)日：2018-03-27

申请号：US15388400

申请日：2016-12-22

Applicant: GLOBALFOUNDRIES INC.

Inventor： Ruilong Xie ,  Chanro Park ,  Andre Labonte ,  Lars Liebmann

IPC: H01L21/768 ,  H01L21/033 ,  H01L29/66 ,  H01L23/535 ,  H01L23/522 ,  H01L23/532

CPC classification number: H01L21/76897 ,  H01L21/0332 ,  H01L21/76805 ,  H01L23/5226 ,  H01L23/5329 ,  H01L23/535 ,  H01L29/66545

Abstract: Disclosed are methods of forming an integrated circuit (IC) structure with self-aligned middle of the line (MOL) contacts and the resulting IC structure. In the methods, different, selectively etchable, dielectric materials are used above the gate level for: a dielectric cap above a gate; a dielectric spacer above a gate sidewall spacer and laterally surrounding the dielectric cap; and a stack of dielectric layer(s) that covers the dielectric cap, the dielectric spacer, and metal plugs positioned laterally adjacent to the dielectric spacer and above source/drain regions. Due to the different dielectric materials, subsequently formed gate and source/drain contacts are self-aligned in two dimensions to provide protection against the occurrence of opens between wires and/or vias in the first BEOL metal level and the contacts and to further provide protection against the occurrence of shorts between the gate contact and any metal plugs and between the source/drain contacts and the gate.

公开(公告)号：US20190392106A1

公开(公告)日：2019-12-26

申请号：US16014287

申请日：2018-06-21

Applicant: GLOBALFOUNDRIES INC.

Inventor： Gregory A. Northrop ,  Lionel Riviere-Cazaux ,  Lars Liebmann ,  Kai Sun ,  Norihito Nakamoto

IPC: G06F17/50 ,  G03F1/36

Abstract: Original cell design rule violations with respect to a second wiring layer are identified, while conductors of the second wiring layer are in an original position. The conductors of the second wiring layer are offset into different offset positions, and then the process of identifying violations is repeated for each of the offset positions. With this, metrics are generated for the original cell for the original position and each of the offset positions. Then, the original cell or the pitch of the second wiring layer are altered to produce alterations. The processes of identifying violations, offsetting conductors in the second wiring layer, repeating the identification of violations for all offsets, and generating metrics are repeated for each of the alterations. The original cell or one of the alterations is then selected, based on which cell produces the lowest number of violations of the design rules.

公开(公告)号：US10468300B2

公开(公告)日：2019-11-05

申请号：US15641927

申请日：2017-07-05

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Ruilong Xie ,  Andre Labonte ,  Lars Liebmann ,  Daniel Chanemougame ,  Chanro Park ,  Nigel Cave ,  Vimal Kamineni

IPC: H01L21/768 ,  H01L21/8234 ,  H01L21/285 ,  H01L21/311 ,  H01L27/088 ,  H01L29/08 ,  H01L23/535 ,  H01L29/06

Abstract: A method of manufacturing a semiconductor device is provided including forming raised source and drain regions on a semiconductor layer, forming a first insulating layer over the semiconductor layer, forming a first contact to one of the source and drain regions in the first insulating layer, forming a second insulating layer over the first contact, forming a trench in the second insulating layer to expose the first contact, removing a portion of the first contact below the trench, thereby forming a recessed surface of the first contact, removing a portion of the first insulating layer, thereby forming a recess in the trench and exposing a portion of a sidewall of the first contact below the recessed surface of the first contact, and filling the trench and the recess formed in the trench with a contact material to form a second contact in contact with the first contact.

公开(公告)号：US20190326286A1

公开(公告)日：2019-10-24

申请号：US15958426

申请日：2018-04-20

Applicant: GLOBALFOUNDRIES INC.

Inventor： Ruilong Xie ,  Steven Soss ,  Steven Bentley ,  Daniel Chanemougame ,  Julien Frougier ,  Bipul Paul ,  Lars Liebmann

IPC: H01L27/092 ,  H01L29/08 ,  H01L29/06 ,  H01L21/8238 ,  H01L21/02 ,  H01L29/66 ,  H01L29/423

Abstract: A semiconductor device at least one first transistor of a first type disposed above a substrate and comprising a channel wider in one cross-section than tall, wherein the first type is a PFET transistor or an NFET transistor; and at least one second transistor of a second type disposed above the at least one first transistor and comprising a channel taller in the one cross-section than wide, wherein the second type is a PFET transistor or an NFET transistor, and the second type is different from the first type. Methods and systems for forming the semiconductor structure.

公开(公告)号：US10304832B1

公开(公告)日：2019-05-28

申请号：US15814440

申请日：2017-11-16

Applicant: GLOBALFOUNDRIES INC.

Inventor： Daniel Chanemougame ,  Lars Liebmann ,  Ruilong Xie

IPC: H01L23/58 ,  H01L27/092 ,  H01L21/8238 ,  H01L29/423 ,  H01L29/417 ,  H01L29/06

Abstract: Disclosed are integrated circuit (IC) structure embodiments that incorporate stacked pair(s) of field effect transistors (FETs) (e.g., gate-all-around FETs), including a lower FET and an upper FET on the lower FET, and various metal components that enable power and/or signal connections to the source/drain regions of those FETs. The metal components can include first buried wire(s) within an isolation region in a level below the stacked pair and a first embedded contact that electrically connects a source/drain region of the lower FET to a first buried wire. Optionally, the metal components can also include second buried wire(s) in dielectric material at the same level as the upper FET and a second embedded contact that electrically connects a source/drain region of the upper FET to a second buried wire. Also disclosed are embodiments of a method of forming such IC structure embodiments.

公开(公告)号：US20190148494A1

公开(公告)日：2019-05-16

申请号：US15814724

申请日：2017-11-16

Applicant: GLOBALFOUNDRIES INC.

Inventor： Ruilong Xie ,  Lars Liebmann ,  Daniel Chanemougame ,  Chanro Park ,  John H. Zhang ,  Steven Bentley ,  Hui Zang

IPC: H01L29/10 ,  H01L29/78 ,  H01L27/24 ,  H01L21/8234

Abstract: A first vertical field effect transistor (VFET) and a second VFET are formed on a substrate. The VFETs are parallel and adjacent to one another, and each comprises: a fin-shaped semiconductor; a lower source/drain (S/D) element; an upper S/D element; and a gate conductor. A portion of a gate conductor of the second VFET that is positioned over a lower S/D element of the second VFET is removed to leave a trench. An isolation spacer is formed to contact the gate conductor of the second VFET in a first portion of the trench. A lower S/D contact of the second VFET is formed on the lower S/D element of the second VFET in a second portion of the trench, a lower S/D contact of the first VFET is formed to a lower S/D element of the first VFET, and contacts are formed.

公开(公告)号：US20190148376A1

公开(公告)日：2019-05-16

申请号：US15814440

申请日：2017-11-16

Applicant: GLOBALFOUNDRIES INC.

Inventor： Daniel Chanemougame ,  Lars Liebmann ,  Ruilong Xie

IPC: H01L27/092 ,  H01L21/8238 ,  H01L29/423 ,  H01L29/06 ,  H01L29/417

Abstract: Disclosed are integrated circuit (IC) structure embodiments that incorporate stacked pair(s) of field effect transistors (FETs) (e.g., gate-all-around FETs), including a lower FET and an upper FET on the lower FET, and various metal components that enable power and/or signal connections to the source/drain regions of those FETs. The metal components can include first buried wire(s) within an isolation region in a level below the stacked pair and a first embedded contact that electrically connects a source/drain region of the lower FET to a first buried wire. Optionally, the metal components can also include second buried wire(s) in dielectric material at the same level as the upper FET and a second embedded contact that electrically connects a source/drain region of the upper FET to a second buried wire. Also disclosed are embodiments of a method of forming such IC structure embodiments.

公开(公告)号：US10283408B2

公开(公告)日：2019-05-07

申请号：US15851774

申请日：2017-12-22

Applicant: GLOBALFOUNDRIES INC.

Inventor： Ruilong Xie ,  Chanro Park ,  Andre Labonte ,  Lars Liebmann

IPC: H01L29/78 ,  H01L21/768 ,  H01L21/033 ,  H01L29/66 ,  H01L23/535 ,  H01L23/522 ,  H01L23/532 ,  H01L29/49

Abstract: Disclosed are methods of forming an integrated circuit (IC) structure with self-aligned middle of the line (MOL) contacts and the resulting IC structure. In the methods, different, selectively etchable, dielectric materials are used above the gate level for: a dielectric cap above a gate; a dielectric spacer above a gate sidewall spacer and laterally surrounding the dielectric cap; and a stack of dielectric layer(s) that covers the dielectric cap, the dielectric spacer, and metal plugs positioned laterally adjacent to the dielectric spacer and above source/drain regions. Due to the different dielectric materials, subsequently formed gate and source/drain contacts are self-aligned in two dimensions to provide protection against the occurrence of opens between wires and/or vias in the first BEOL metal level and the contacts and to further provide protection against the occurrence of shorts between the gate contact and any metal plugs and between the source/drain contacts and the gate.