公开(公告)号：US09443956B2

公开(公告)日：2016-09-13

申请号：US14675880

申请日：2015-04-01

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Hong Yu ,  Biao Zuo ,  Jin Ping Liu ,  Huang Liu

IPC: H01L29/66

CPC classification number: H01L29/6656 ,  H01L29/4991 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/785

Abstract: A method includes forming a line feature above a substrate. Carbon-containing spacers are formed on sidewalls of the line feature. A first dielectric layer is formed above the carbon spacers and the line feature. The first dielectric layer is planarized to expose upper ends of the carbon-containing spacers. An ashing process is performed to remove the carbon-containing spacers and define air gaps adjacent the line feature. A cap layer is formed to seal the upper ends of the air gaps.

Abstract translation: 一种方法包括在衬底上形成线特征。 含碳隔离物形成在线特征的侧壁上。 第一电介质层形成在碳间隔物和线特征之上。 平面化第一介电层以暴露含碳间隔物的上端。 执行灰化处理以除去含碳间隔物并限定与线特征相邻的气隙。 形成盖层以密封气隙的上端。

公开(公告)号：US09419126B2

公开(公告)日：2016-08-16

申请号：US13835944

申请日：2013-03-15

Applicant: GLOBALFOUNDRIES, Inc.

Inventor： Xiaodong Yang ,  Jin Ping Liu ,  Yanxiang Liu ,  Xusheng Wu

IPC: H01L29/78 ,  H01L21/8238 ,  H01L29/66 ,  H01L29/165

CPC classification number: H01L29/78 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823878 ,  H01L29/165 ,  H01L29/66636 ,  H01L29/7848

Abstract: Integrated circuits and methods for fabricating integrated circuits are provided. In an embodiment, a semiconductor substrate includes a shallow trench isolation structure disposed therein. A gate electrode structure overlies semiconductor material of the semiconductor substrate. A first sidewall spacer is formed adjacent to the gate electrode structure, with a first surface of the shallow trench isolation structure exposed and spaced from the first sidewall spacer by a region of the semiconductor material. The first surface of the shallow trench isolation structure is masked with an isolation structure mask. The region of the semiconductor material is free from the isolation structure mask. A recess is etched in the region of the semiconductor material, with the isolation structure mask in place. A semiconductor material is epitaxially grown within the recess to form an epitaxially-grown semiconductor region adjacent to the gate electrode structure.

Abstract translation: 提供了用于制造集成电路的集成电路和方法。 在一个实施例中，半导体衬底包括设置在其中的浅沟槽隔离结构。 栅电极结构覆盖半导体衬底的半导体材料。 形成与栅电极结构相邻的第一侧壁间隔物，其中浅沟槽隔离结构的第一表面暴露并与第一侧壁间隔物隔开半导体材料的区域。 浅沟槽隔离结构的第一表面用隔离结构掩模掩蔽。 半导体材料的区域没有隔离结构掩模。 在半导体材料的区域中蚀刻凹陷，隔离结构掩模就位。 半导体材料在凹槽内外延生长以形成与栅电极结构相邻的外延生长的半导体区域。

公开(公告)号：US20160163816A1

公开(公告)日：2016-06-09

申请号：US14675880

申请日：2015-04-01

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Hong Yu ,  Biao Zuo ,  Jin Ping Liu ,  Huang Liu

IPC: H01L29/66

CPC classification number: H01L29/6656 ,  H01L29/4991 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/785

Abstract: A method includes forming a line feature above a substrate. Carbon-containing spacers are formed on sidewalls of the line feature. A first dielectric layer is formed above the carbon spacers and the line feature. The first dielectric layer is planarized to expose upper ends of the carbon-containing spacers. An ashing process is performed to remove the carbon-containing spacers and define air gaps adjacent the line feature. A cap layer is formed to seal the upper ends of the air gaps.

Abstract translation: 一种方法包括在衬底上形成线特征。 含碳隔离物形成在线特征的侧壁上。 第一电介质层形成在碳间隔物和线特征之上。 平面化第一介电层以暴露含碳间隔物的上端。 执行灰化处理以除去含碳间隔物并限定与线特征相邻的气隙。 形成盖层以密封气隙的上端。

公开(公告)号：US09362180B2

公开(公告)日：2016-06-07

申请号：US14189085

申请日：2014-02-25

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Bongki Lee ,  Jin Ping Liu ,  Manoj Joshi ,  Manfred Eller ,  Rohit Pal ,  Richard J. Carter ,  Srikanth Balaji Samavedam

IPC: H01L21/8238 ,  H01L21/8234 ,  H01L27/088 ,  H01L29/49 ,  H01L21/28 ,  H01L27/092

CPC classification number: H01L21/823842 ,  H01L21/28088 ,  H01L21/823431 ,  H01L21/82345 ,  H01L27/088 ,  H01L27/0886 ,  H01L27/092 ,  H01L27/0922 ,  H01L27/0924 ,  H01L29/4966 ,  H01L29/66545

Abstract: In one aspect there is set forth herein an integrated circuit having a first plurality of field effect transistors and a second plurality of field effect transistor, wherein field effect transistors of the first plurality of field effect transistors each have a first gate stack and wherein field effect transistors of the second plurality of field effect transistors each have a second gate stack, the second gate stack being different from the first gate stack by having a metal layer common to the first gate stack and the second gate stack that includes a first thickness at the first gate stack and a second thickness at the second gate stack.

Abstract translation: 在一个方面，这里提出了具有第一多个场效应晶体管和第二多个场效应晶体管的集成电路，其中第一多个场效应晶体管的场效应晶体管各自具有第一栅极堆叠，并且其中场效应 第二多个场效应晶体管的晶体管每个都具有第二栅极堆叠，第二栅极堆叠通过具有与第一栅极堆叠共同的金属层与第一栅极堆叠而不同于第一栅极堆叠，第二栅极堆叠包括第一栅极堆叠的第一厚度 第一栅极堆叠和第二栅极堆叠处的第二厚度。

公开(公告)号：US09236481B1

公开(公告)日：2016-01-12

申请号：US14699543

申请日：2015-04-29

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Hui Zang ,  Jin Ping Liu

IPC: H01L27/088 ,  H01L29/78 ,  H01L29/49 ,  H01L29/06 ,  H01L29/66 ,  H01L21/027 ,  H01L21/311 ,  H01L21/306 ,  H01L21/308 ,  H01L21/3213

CPC classification number: H01L29/7851 ,  H01L21/0337 ,  H01L21/28123 ,  H01L21/3086 ,  H01L21/3105 ,  H01L21/32139 ,  H01L29/66545 ,  H01L29/66795

Abstract: Semiconductor devices and methods for forming devices with ultraviolet curing. One method includes, for instance: obtaining a wafer; forming at least one mandrel; forming spacers adjacent to the at least one mandrel; performing an ultraviolet treatment to at least one set of spacers; and etching to form hard mask regions below at least the spacers. An intermediate semiconductor device includes, for instance: a substrate; a stop layer over the substrate; a first barrier layer over the stop layer; at least one first mandrel and at least one second mandrel on the first barrier layer; at least one first set of spacers positioned adjacent to the first mandrel; at least one second set of spacers positioned adjacent to the second mandrel; and a second barrier layer over the at least one first mandrel and the at least one first set of spacers.

Abstract translation: 用于形成紫外线固化装置的半导体装置和方法。 一种方法包括，例如：获得晶片; 形成至少一个心轴; 形成邻近所述至少一个心轴的间隔件; 对至少一组间隔件执行紫外线处理; 并蚀刻以至少形成间隔物以形成硬掩模区域。 中间半导体器件包括例如：衬底; 在衬底上的停止层; 停止层上的第一阻挡层; 至少一个第一心轴和所述第一阻挡层上的至少一个第二心轴; 位于第一心轴附近的至少一个第一组间隔件; 至少一个第二组间隔件邻近第二心轴定位; 以及在所述至少一个第一心轴和所述至少一个第一组间隔物上的第二阻挡层。

公开(公告)号：US09230822B1

公开(公告)日：2016-01-05

申请号：US14306920

申请日：2014-06-17

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Hong Yu ,  Haigou Huang ,  Jin Ping Liu ,  Huang Liu

IPC: H01L21/3105 ,  H01L21/311 ,  H01L21/02

CPC classification number: H01L21/31055 ,  H01L21/02318 ,  H01L21/02326 ,  H01L21/0234 ,  H01L21/31051 ,  H01L21/31111 ,  H01L21/823821 ,  H01L21/823842

Abstract: A semiconductor structure with mixed n-type and p-type non-planar transistors includes a residual overlapping mask bump on one or more of the dummy gates. A dielectric layer is created over the structure having a top surface above the residual bump, for example, using a blanket deposition and chemical-mechanical underpolish (i.e., stopping before exposing the gate cap). The residual bump is then transformed into a same material as the dielectric, either in its entirety and then removing the combined dielectric, or by removing the dielectric first and partly removing the residual bump, the remainder of which is then transformed and the dielectric removed. In either case, the structure is planarized for further processing.

Abstract translation: 具有混合n型和p型非平面晶体管的半导体结构包括在一个或多个虚拟栅极上的残留重叠掩模凸块。 例如，使用覆盖沉积和化学机械的低估（即，在暴露栅极盖之前停止），在该结构上方形成介电层，该顶表面具有顶部表面。 然后将剩余的凸块转变成与电介质完全相同的材料，然后去除组合的电介质，或者通过首先去除电介质并部分去除残余凸块，然后将其余部分转化并除去电介质。 在任一种情况下，将结构平坦化用于进一步处理。

公开(公告)号：US20150287824A1

公开(公告)日：2015-10-08

申请号：US14244322

申请日：2014-04-03

Applicant: GLOBALFOUNDRIES, Inc.

Inventor： Shishir Ray ,  Jin Ping Liu ,  Bharat Krishnan

IPC: H01L29/78 ,  H01L29/66 ,  H01L29/161 ,  H01L21/268 ,  H01L21/265 ,  H01L29/167

CPC classification number: H01L21/268 ,  H01L21/26513 ,  H01L29/161 ,  H01L29/167 ,  H01L29/78 ,  H01L29/7847

Abstract: Integrated circuits with stressed semiconductor substrates, processes for preparing stressed semiconductor substrates, and processes for preparing integrated circuits including stressed semiconductor substrates are provided herein. An exemplary process for preparing a stressed semiconductor substrate includes providing a semiconductor substrate of a semiconductor material having a first crystalline lattice constant; introducing a dopant on and into a surface layer of the semiconductor substrate via ion implantation at an amount above a solubility limit of the dopant in the semiconductor material to form a dopant-containing surface layer of the semiconductor substrate; applying energy to the dopant-containing surface layer of the semiconductor substrate with an ultra-short pulse laser to form a molten semiconductor:dopant layer on a surface of the semiconductor substrate; and removing the energy such that the molten semiconductor:dopant layer forms a solid semiconductor:dopant layer with a second crystalline lattice having a second lattice constant that differs from the first lattice constant.

Abstract translation: 具有应力半导体衬底的集成电路，制备受压半导体衬底的工艺，以及制备包括应力半导体衬底的集成电路的工艺。 制备应力半导体衬底的示例性方法包括提供具有第一晶格常数的半导体材料的半导体衬底; 在半导体材料中以高于掺杂剂的溶解度极限的量经由离子注入在半导体衬底的表面层上引入掺杂剂，以形成半导体衬底的掺杂剂表面层; 用超短脉冲激光对半导体衬底的掺杂剂表面层施加能量，以在半导体衬底的表面上形成熔融半导体：掺杂剂层; 并且去除能量，使得熔融半导体：掺杂剂层形成固体半导体：具有与第一晶格常数不同的第二晶格常数的第二晶格的掺杂剂层。

公开(公告)号：US09076645B1

公开(公告)日：2015-07-07

申请号：US14272554

申请日：2014-05-08

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Shishir Ray ,  Sandeep Gaan ,  Jin Ping Liu ,  Zhiguo Sun

IPC: H01L21/31 ,  H01L21/02

CPC classification number: H01L21/02112 ,  H01L21/02123 ,  H01L21/02203 ,  H01L21/02216 ,  H01L21/02255 ,  H01L21/76811 ,  H01L21/76813 ,  H01L21/7682 ,  H01L21/76828 ,  H01L2221/1047

Abstract: Circuit structure fabrication methods are provided which include: providing an interlayer structure above a substrate, the interlayer structure including porogens dispersed within a dielectric material; and pulse laser annealing the interlayer structure to form a treated interlayer structure, the pulse laser annealing polymerizing the dielectric material of the interlayer structure to form a polymeric dielectric material, that includes pores disposed therein. The pulse laser annealing facilitates increasing elasticity modulus of the treated interlayer structure by, in part, maintaining structural integrity of the treated interlayer structure, notwithstanding that there are pores disposed within the polymeric dielectric material which, for instance, facilitates reducing dielectric constant of the treated interlayer structure.

Abstract translation: 提供了电路结构制造方法，其包括：在基底之上提供层间结构，所述层间结构包括分散在电介质材料内的致孔剂; 并且脉冲激光退火层间结构以形成经处理的层间结构，脉冲激光退火聚合层间结构的电介质材料以形成聚合物电介质材料，其包括设置在其中的孔。 脉冲激光退火有助于通过部分地维持经处理的层间结构的结构完整性来提高经处理的层间结构的弹性模量，尽管在聚合物电介质材料内设置孔，其例如有助于降低经处理的层间结构的介电常数 夹层结构。