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    Tantalum carbide metal gate stack for mid-gap work function applications
    32.
    发明申请
    Tantalum carbide metal gate stack for mid-gap work function applications 审中-公开
    用于中间隙功能应用的钽硬质合金金属栅极叠层

    公开(公告)号：US20160093711A1

    公开(公告)日：2016-03-31

    申请号：US14315079

    申请日：2014-06-25

    Applicant: Intermolecular Inc. ,  GLOBALFOUNDRIES, Inc.

    Inventor： Zhendong Hong ,  Paul Besser ,  Kisik Choi ,  Amol Joshi ,  Olov Karlsson ,  Susie Tzeng

    IPC: H01L29/49 ,  H01L21/285 ,  H01L29/423 ,  H01L21/28

    CPC classification number: H01L29/4966 ,  H01L21/28088 ,  H01L21/28185 ,  H01L29/513 ,  H01L29/517 ,  H01L29/66795 ,  H01L29/785

    Abstract: Devices with lightly-doped semiconductor channels (e.g., FinFETs) need mid-gap (˜4.6-4.7 eV) work-function layers, preferably with low resistivity and a wide process window, in the gate stack. Tantalum carbide (TaC) has a mid-gap work function that is insensitive to thickness. TaC can be deposited with good adhesion on high-k materials or on optional metal-nitride cap layers. TaC can also serve as the fill metal, or it can be used with other fills such as tungsten (W) or aluminum (Al). The TaC may be sputtered from a TaC target, deposited by ALD or CVD using TaCl4 and TMA, or produced by methane treatment of deposited Ta. Al may be added to tune the threshold voltage.

    Abstract translation: 具有轻掺杂半导体通道（例如，FinFET）的器件在栅极堆叠中需要中间隙（〜4.6-6.7eV）的功函数层，优选地具有低电阻率和宽的工艺窗口。 碳化钽（TaC）具有对厚度不敏感的中间间隙功能。 可以在高k材料或任选的金属氮化物盖层上沉积具有良好粘附性的TaC。 TaC也可以作为填充金属，也可以与钨（W）或铝（Al）等其他填料一起使用。 TaC可以从TaC靶溅射，通过ALD或CVD使用TaCl4和TMA沉积，或通过沉积的Ta的甲烷处理产生。 可以添加Al来调节阈值电压。

    Atomic Layer Deposition of HfAlC as a Metal Gate Workfunction Material in MOS Devices
    33.
    发明申请
    Atomic Layer Deposition of HfAlC as a Metal Gate Workfunction Material in MOS Devices 有权
    HfAlC作为MOS器件中金属栅极功能材料的原子层沉积

    公开(公告)号：US20160035631A1

    公开(公告)日：2016-02-04

    申请号：US14094691

    申请日：2013-12-02

    Applicant: GLOBALFOUNDRIES, INC. ,  INTERMOLECULAR INC.

    Inventor： Albert Sanghyup Lee ,  Paul Besser ,  Kisik Choi ,  Edward L Haywood ,  Hoon Kim ,  Salil Mujumdar

    IPC: H01L21/66 ,  H01L21/28

    CPC classification number: H01L22/10 ,  H01L21/28088 ,  H01L21/28158 ,  H01L21/28194 ,  H01L22/12 ,  H01L22/14 ,  H01L22/20 ,  H01L29/4966 ,  H01L29/517 ,  H01L29/665 ,  H01L29/6659 ,  H01L29/94

    Abstract: ALD of HfxAlyCz films using hafnium chloride (HfCl4) and Trimethylaluminum (TMA) precursors can be combined with post-deposition anneal processes and ALD liners to control the device characteristics in high-k metal-gate devices. Variation of the HfCl4 pulse time allows for control of the Al % incorporation in the HfxAlyCz film in the range of 10-13%. Combinatorial process tools can be employed for rapid electrical and materials characterization of various materials stacks. The effective work function (EWF) in metal oxide semiconductor capacitor (MOSCAP) devices with the HfxAlyCz work function layer coupled with ALD deposited HfO2 high-k gate dielectric layers was quantified to be mid-gap at ˜4.6 eV. Thus, HfxAlyCz is a promising metal gate work function material allowing for the tuning of device threshold voltages (Vth) for anticipated multi-Vth integrated circuit (IC) devices.

    Abstract translation: 使用氯化铪（HfCl4）和三甲基铝（TMA）前体的HfxAlyCz膜的ALD可与后沉积退火工艺和ALD衬垫组合以控制高k金属栅极器件中的器件特性。 HfCl 4脉冲时间的变化允许控制HfxAlyCz膜中的Al％掺入在10-13％的范围内。 组合工艺工具可用于各种材料堆的快速电气和材料表征。 金属氧化物半导体电容器（MOSCAP）器件中具有HfxAlyCz功函数层与ALD沉积HfO 2高k栅极电介质层耦合的有效功函数（EWF）被定义为〜4.6eV的中间间隙。 因此，HfxAlyCz是有希望的金属栅极功能材料，允许调谐预期的多Vth集成电路（IC）器件的器件阈值电压（Vth）。

    Integrated circuits having improved high-K dielectric layers and methods for fabrication of same
    35.
    发明授权
    Integrated circuits having improved high-K dielectric layers and methods for fabrication of same 有权
    具有改进的高K电介质层的集成电路及其制造方法

    公开(公告)号：US09224610B2

    公开(公告)日：2015-12-29

    申请号：US13931205

    申请日：2013-06-28

    Applicant: GLOBALFOUNDRIES, Inc.

    Inventor： Hoon Kim ,  Kisik Choi

    IPC: H01L21/336 ,  H01L21/28 ,  H01L29/51 ,  H01L21/02 ,  H01L29/66

    CPC classification number: H01L21/28229 ,  H01L21/02181 ,  H01L21/022 ,  H01L21/28185 ,  H01L29/513 ,  H01L29/517 ,  H01L29/66545

    Abstract: Integrated circuits and methods for fabricating integrated circuits are provided. In accordance with an exemplary embodiment, a method for fabricating an integrated circuit includes exposing a portion of a surface of a semiconductor substrate between a first spacer and a second spacer. The method further includes selectively forming a dielectric layer on the portion of the surface. A metal gate is formed over the dielectric layer and between the first spacer and the second spacer. The metal gate contacts the first spacer and the second spacer.

    Abstract translation: 提供了用于制造集成电路的集成电路和方法。 根据示例性实施例，用于制造集成电路的方法包括将半导体衬底的表面的一部分暴露在第一间隔物和第二间隔物之间​​。 该方法还包括在表面的该部分上选择性地形成介电层。 金属栅极形成在电介质层之上并且在第一间隔物和第二间隔物之间​​。 金属栅极接触第一间隔物和第二间隔物。

    COMMON FABRICATION OF DIFFERENT SEMICONDUCTOR DEVICES WITH DIFFERENT THRESHOLD VOLTAGES
    37.
    发明申请
    COMMON FABRICATION OF DIFFERENT SEMICONDUCTOR DEVICES WITH DIFFERENT THRESHOLD VOLTAGES 审中-公开
    具有不同阈值电压的不同半导体器件的通用制造

    公开(公告)号：US20150179640A1

    公开(公告)日：2015-06-25

    申请号：US14134358

    申请日：2013-12-19

    Applicant: GLOBALFOUNDRIES Inc.

    Inventor： Hoon Kim ,  Kisik Choi ,  Jae Young Lee

    IPC: H01L27/088 ,  H01L21/28 ,  H01L21/265 ,  H01L21/223 ,  H01L21/8234 ,  H01L29/51

    CPC classification number: H01L21/28158 ,  H01L21/28079 ,  H01L21/28088 ,  H01L21/823842 ,  H01L21/823857 ,  H01L27/092 ,  H01L29/66545

    Abstract: A multi-device semiconductor structure including a p-type logic device, a p-type memory device, a n-type logic device and a n-type memory device are provided on a bulk silicon substrate. Each of these devices includes a dielectric layer and either a n-type or a p-type work function layer disposed over the dielectric layer. Some of the various device types of the multi-device semiconductor structure are protected, and impurities, such as aluminum and/or nitrogen, are added to the exposed work function layers to achieve one or more other desired work functions with different threshold voltages.

    Abstract translation: 包括p型逻辑器件，p型存储器件，n型逻辑器件和n型存储器件的多器件半导体结构设置在体硅衬底上。 这些器件中的每一个包括电介质层和设置在电介质层上的n型或p型功函数层。 多器件半导体结构的各种器件类型中的一些被保护，并且诸如铝和/或氮的杂质被添加到暴露的功函数层中以实现具有不同阈值电压的一个或多个其它期望的功函数。

    Methods of forming gate structures with multiple work functions and the resulting products
    39.
    发明授权
    Methods of forming gate structures with multiple work functions and the resulting products 有权
    形成具有多种功能的门结构的方法以及所得到的产品

    公开(公告)号：US09012319B1

    公开(公告)日：2015-04-21

    申请号：US14069782

    申请日：2013-11-01

    Applicant: GLOBALFOUNDRIES Inc.

    Inventor： Kisik Choi ,  Hoon Kim

    IPC: H01L21/3205 ,  H01L21/28 ,  H01L29/51

    CPC classification number: H01L21/28158 ,  H01L21/28185 ,  H01L21/28247 ,  H01L21/823842 ,  H01L21/823857 ,  H01L29/4966 ,  H01L29/512 ,  H01L29/517 ,  H01L29/66545

    Abstract: One illustrative method disclosed herein includes removing sacrificial gate structures for NMOS and PMOS transistors to thereby define NMOS and PMOS gate cavities, forming a high-k gate insulation layer in the NMOS and PMOS gate cavities, forming a lanthanide-based material layer on the high-k gate insulation layer in the NMOS and PMOS gate cavities, performing a heating process to drive material from the lanthanide-based material layer into the high-k gate insulation layer so as to thereby form a lanthanide-containing high-k gate insulation layer in each of the NMOS and PMOS gate cavities, and forming gate electrode structures above the lanthanide-containing high-k gate insulation layer in the NMOS and PMOS gate cavities.

    Abstract translation: 本文公开的一种说明性方法包括去除用于NMOS和PMOS晶体管的牺牲栅极结构，从而限定NMOS和PMOS栅极空腔，在NMOS和PMOS栅极腔中形成高k栅绝缘层，在高层上形成镧系元素基材料层 -k栅极绝缘层，执行加热处理以将材料从镧系元素基材料层驱动到高k栅极绝缘层中，从而形成含镧系元素的高k栅极绝缘层 在每个NMOS和PMOS栅极腔中，以及在NMOS和PMOS栅极腔中的含镧系元素的高k栅极绝缘层之上形成栅电极结构。

    INTEGRATED CIRCUITS HAVING IMPROVED HIGH-K DIELECTRIC LAYERS AND METHODS FOR FABRICATION OF SAME
    40.
    发明申请
    INTEGRATED CIRCUITS HAVING IMPROVED HIGH-K DIELECTRIC LAYERS AND METHODS FOR FABRICATION OF SAME 有权
    具有改进的高K介电层的集成电路及其制造方法

    公开(公告)号：US20150001643A1

    公开(公告)日：2015-01-01

    申请号：US13931205

    申请日：2013-06-28

    Applicant: GlobalFoundries, Inc.

    Inventor： Hoon Kim ,  Kisik Choi

    IPC: H01L21/28 ,  H01L29/51

    CPC classification number: H01L21/28229 ,  H01L21/02181 ,  H01L21/022 ,  H01L21/28185 ,  H01L29/513 ,  H01L29/517 ,  H01L29/66545

    Abstract: Integrated circuits and methods for fabricating integrated circuits are provided. In accordance with an exemplary embodiment, a method for fabricating an integrated circuit includes exposing a portion of a surface of a semiconductor substrate between a first spacer and a second spacer. The method further includes selectively forming a dielectric layer on the portion of the surface. A metal gate is formed over the dielectric layer and between the first spacer and the second spacer. The metal gate contacts the first spacer and the second spacer.

    Abstract translation: 提供了用于制造集成电路的集成电路和方法。 根据示例性实施例，用于制造集成电路的方法包括将半导体衬底的表面的一部分暴露在第一间隔物和第二间隔物之间​​。 该方法还包括在表面的该部分上选择性地形成介电层。 金属栅极形成在电介质层之上并且在第一间隔物和第二间隔物之间​​。 金属栅极接触第一间隔物和第二间隔物。

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