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    Field effect transistors having multiple stacked channels
    31.
    发明授权
    Field effect transistors having multiple stacked channels 有权
    具有多个堆叠通道的场效应晶体管

    公开(公告)号：US07002207B2

    公开(公告)日：2006-02-21

    申请号：US10610607

    申请日：2003-07-01

    申请人： Sung-Min Kim ,  Dong-Gun Park ,  Chang-Sub Lee ,  Jeong-Dong Choe ,  Shin-Ae Lee ,  Seong-Ho Kim

    发明人： Sung-Min Kim ,  Dong-Gun Park ,  Chang-Sub Lee ,  Jeong-Dong Choe ,  Shin-Ae Lee ,  Seong-Ho Kim

    IPC分类号： H01L29/76 ,  H01L29/94

    CPC分类号： H01L29/785 ,  H01L21/823412 ,  H01L29/42356 ,  H01L29/42384 ,  H01L29/42392 ,  H01L29/66477 ,  H01L29/66545 ,  H01L29/66636 ,  H01L29/66772 ,  H01L29/66787 ,  H01L29/78 ,  H01L29/78642 ,  H01L29/78654 ,  H01L29/78696

    摘要： Integrated circuit field effect transistor devices include a substrate having a surface and an active channel pattern on the surface. The active channel pattern includes channels that are stacked upon one another and are spaced apart from one another to define at least one tunnel between adjacent channels. A gate electrode surrounds the channels and extends through the at least one tunnel. A pair of source/drain regions also is provided. Integrated circuit field effect transistors are manufactured, by forming a pre-active pattern on a surface of a substrate. The pre-active pattern includes a series of interchannel layers and channel layers stacked alternately upon each other. Source/drain regions are formed on the substrate at opposite ends of the pre-active pattern. The interchannel layers are selectively removed to form tunnels. A gate electrode is formed in the tunnels and surrounding the channels.

    摘要翻译： 集成电路场效应晶体管器件包括在表面上具有表面和有源沟道图案的衬底。 活动通道图案包括彼此堆叠并且彼此间隔开以限定相邻通道之间的至少一个通道的通道。 栅电极围绕通道并延伸穿过至少一个通道。 还提供了一对源极/漏极区域。 通过在衬底的表面上形成预活性图案来制造集成电路场效应晶体管。 预激活图案包括彼此交替堆叠的一系列通道间层和沟道层。 源极/漏极区域在预活化图案的相对端处在衬底上形成。 选择性地去除通道间层以形成隧道。 在隧道中形成栅电极并围绕通道。

    Semiconductor devices having a field effect transistor and methods of fabricating the same
    32.
    发明申请
    Semiconductor devices having a field effect transistor and methods of fabricating the same 有权
    具有场效应晶体管的半导体器件及其制造方法

    公开(公告)号：US20050227424A1

    公开(公告)日：2005-10-13

    申请号：US11090740

    申请日：2005-03-24

    申请人： Chang-Woo Oh ,  Dong-Gun Park ,  Dong-Won Kim ,  Jeong-Dong Choe

    发明人： Chang-Woo Oh ,  Dong-Gun Park ,  Dong-Won Kim ,  Jeong-Dong Choe

    IPC分类号： H01L29/78 ,  H01L21/336 ,  H01L21/8234 ,  H01L29/06 ,  H01L29/786

    CPC分类号： H01L29/785 ,  H01L29/0653 ,  H01L29/66795 ,  H01L29/7851 ,  H01L29/78687 ,  Y10S438/933

    摘要： A semiconductor device having a field effect transistor and a method of forming the same are provided. The semiconductor device preferably includes a device active pattern disposed on a predetermined region of the substrate. The gate electrode preferably crosses over the device active pattern, interposed by a gate insulation layer. A support pattern is preferably interposed between the device active pattern and the substrate. The support pattern can be disposed under the gate electrode. A filling insulation pattern is preferably disposed between the device active pattern and the filling insulation pattern. The filling insulation pattern may be disposed under the source/drain region. A device active pattern under the gate electrode is preferably formed of a strained silicon having a lattice width wider than a silicon lattice.

    摘要翻译： 提供具有场效应晶体管的半导体器件及其形成方法。 半导体器件优选地包括设置在衬底的预定区域上的器件有源图案。 栅电极优选地跨过器件有源图案，由栅极绝缘层插入。 支撑图案优选地插入在器件活性图案和基底之间。 支撑图案可以设置在栅电极下方。 填充绝缘图案优选地设置在装置活性图案和填充绝缘图案之间。 填充绝缘图案可以设置在源极/漏极区域下方。 栅电极下方的器件有源图案优选由具有比硅晶格宽的晶格宽度的应变硅形成。

    Methods of forming field effect transistors including raised source/drain regions
    33.
    发明授权
    Methods of forming field effect transistors including raised source/drain regions 有权
    形成包括升高的源极/漏极区域的场效应晶体管的方法

    公开(公告)号：US06951785B2

    公开(公告)日：2005-10-04

    申请号：US10832080

    申请日：2004-04-26

    申请人： Chang-Woo Oh ,  Dong-Gun Park ,  Jeong-Dong Choe ,  Chang-Sub Lee

    发明人： Chang-Woo Oh ,  Dong-Gun Park ,  Jeong-Dong Choe ,  Chang-Sub Lee

    IPC分类号： H01L21/336

    CPC分类号： H01L29/66621 ,  H01L29/66537 ,  H01L29/66553

    摘要： A method of forming a field effect transistor may include forming a doped layer at a surface of a semiconductor substrate, and forming a groove through the doped layer at the surface of the semiconductor substrate while maintaining portions of the doped layer on opposite sides of the groove. A gate insulating layer may be formed on a surface of the groove, and a gate electrode may be formed on the gate insulating layer in the groove.

    摘要翻译： 形成场效应晶体管的方法可以包括在半导体衬底的表面上形成掺杂层，并且在半导体衬底的表面上形成通过掺杂层的沟槽，同时保持掺杂层在槽的相对侧上的部分 。 可以在沟槽的表面上形成栅极绝缘层，并且可以在沟槽中的栅极绝缘层上形成栅电极。

    Nonvolatile semiconductor device including a floating gate and associated systems
    34.
    发明授权
    Nonvolatile semiconductor device including a floating gate and associated systems 有权
    包括浮动栅极和相关系统的非易失性半导体器件

    公开(公告)号：US08330205B2

    公开(公告)日：2012-12-11

    申请号：US13040380

    申请日：2011-03-04

    申请人： Se-Hoon Lee ,  Donghoon Jang ,  Jong Jin Lee ,  Jeong-Dong Choe

    发明人： Se-Hoon Lee ,  Donghoon Jang ,  Jong Jin Lee ,  Jeong-Dong Choe

    IPC分类号： H01L29/788

    CPC分类号： H01L29/42324 ,  H01L21/28273 ,  H01L29/66825 ,  H01L29/7881

    摘要： A memory device includes a first floating gate electrode on a substrate between adjacent isolation layers in the substrate, at least a portion of the first floating gate protruding above a portion of the adjacent isolation layers, a second floating gate electrode, electrically connected to the first floating gate electrode, on at least one of the adjacent isolation layers, a dielectric layer over the first and second floating gate electrodes, and a control gate over the dielectric layer and the first and second floating gate electrodes.

    摘要翻译： 存储器件包括在衬底中相邻隔离层之间的衬底上的第一浮置栅电极，第一浮置栅极的至少一部分突出在相邻隔离层的一部分上方，第二浮栅电极电连接到第一浮栅 浮栅电极，在至少一个相邻的隔离层上，第一和第二浮置栅电极之上的电介质层，以及介电层上的控制栅极以及第一和第二浮栅电极。

    Synchronous pulse plasma etching equipment and method of fabricating a semiconductor device
    36.
    发明申请
    Synchronous pulse plasma etching equipment and method of fabricating a semiconductor device 有权
    同步脉冲等离子体蚀刻设备及制造半导体器件的方法

    公开(公告)号：US20100130018A1

    公开(公告)日：2010-05-27

    申请号：US12591602

    申请日：2009-11-24

    申请人： Ken Tokashiki ,  Hong Cho ,  Jeong-Dong Choe

    发明人： Ken Tokashiki ,  Hong Cho ,  Jeong-Dong Choe

    IPC分类号： H01L21/3065

    CPC分类号： H01J37/32165 ,  H01J37/32082 ,  H01J37/32174

    摘要： Synchronous pulse plasma etching equipment includes a first electrode and one or more second electrodes configured to generate plasma in a plasma etching chamber. A first radio frequency power output unit is configured to apply a first radio frequency power having a first frequency and a first duty ratio to the first electrode, and to output a control signal including information about a phase of the first radio frequency power. At least one second radio frequency power output unit is configured to apply a second radio frequency power having a second frequency and a second duty ratio to a corresponding second electrode among the second electrodes. The second radio frequency power output unit is configured to control the second radio frequency power to be synchronized with the first radio frequency power or to have a phase difference from the first radio frequency power in response to the control signal.

    摘要翻译： 同步脉冲等离子体蚀刻设备包括第一电极和被配置为在等离子体蚀刻室中产生等离子体的一个或多个第二电极。 第一射频功率输出单元被配置为向第一电极施加具有第一频率和第一占空比的第一射频功率，并且输出包括关于第一射频功率的相位的信息的控制信号。 至少一个第二射频功率输出单元被配置为将具有第二频率和第二占空比的第二射频功率应用于第二电极中的对应的第二电极。 第二射频功率输出单元被配置为响应于控制信号控制与第一射频功率同步的第二射频功率或者与第一射频功率相位差。

    SEMICONDUCTOR-ON-INSULATOR (SOI) DEVICES USING VOID SPACES
    37.
    发明申请
    SEMICONDUCTOR-ON-INSULATOR (SOI) DEVICES USING VOID SPACES 审中-公开
    半导体绝缘体（SOI）器件使用空隙

    公开(公告)号：US20100127328A1

    公开(公告)日：2010-05-27

    申请号：US12696125

    申请日：2010-01-29

    申请人： Chang-Woo Oh ,  Dong-Gun Park ,  Sung-Young Lee ,  Jeong-Dong Choe

    发明人： Chang-Woo Oh ,  Dong-Gun Park ,  Sung-Young Lee ,  Jeong-Dong Choe

    IPC分类号： H01L27/12

    CPC分类号： H01L29/785 ,  H01L21/7624 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/66795 ,  H01L29/78603

    摘要： An SOI substrate is fabricated by providing a substrate having a sacrificial layer thereon, an active semiconductor layer on the sacrificial layer remote from the substrate and a supporting layer that extends along at least two sides of the active semiconductor layer and the sacrificial layer and onto the substrate, and that exposes at least one side of the sacrificial layer. At least some of the sacrificial layer is etched through the at least one side thereof that is exposed by the supporting layer to form a void space between the substrate and the active semiconductor layer, such that the active semiconductor layer is supported in spaced-apart relation from the substrate by the supporting layer. The void space may be at least partially filled with an insulator lining.

    摘要翻译： 通过在其上提供具有牺牲层的衬底，在远离衬底的牺牲层上的有源半导体层和沿着有源半导体层和牺牲层的至少两侧延伸的支撑层来制造SOI衬底 衬底，并且暴露出牺牲层的至少一侧。 牺牲层中的至少一部分被蚀刻穿过其至少一侧，其被支撑层暴露以在衬底和有源半导体层之间形成空隙，使得有源半导体层以间隔的关系支撑 通过支撑层从衬底。 空隙空间可以至少部分地填充有绝缘体衬里。

    Methods of fabricating multichannel metal oxide semiconductor (MOS) transistors
    38.
    发明授权
    Methods of fabricating multichannel metal oxide semiconductor (MOS) transistors 有权
    制造多通道金属氧化物半导体（MOS）晶体管的方法

    公开(公告)号：US07670912B2

    公开(公告)日：2010-03-02

    申请号：US10797463

    申请日：2004-03-10

    申请人： Kyoung-Hwan Yeo ,  Dong-Gun Park ,  Jeong-Dong Choe

    发明人： Kyoung-Hwan Yeo ,  Dong-Gun Park ,  Jeong-Dong Choe

    IPC分类号： H01L21/336

    CPC分类号： H01L29/66484 ,  H01L21/8221 ,  H01L21/823412 ,  H01L27/0688 ,  H01L29/7831

    摘要： Unit cells of metal oxide semiconductor (MOS) transistors are provided including an integrated circuit substrate an a MOS transistor on the integrated circuit substrate. The MOS transistor includes a source region, a drain region and a gate. The gate is positioned between the source region and the drain region. A horizontal channel is provided between the source and drain regions. The horizontal channel includes at least two spaced apart horizontal channel regions. Related methods of fabricating MOS transistors are also provided.

    摘要翻译： 提供金属氧化物半导体（MOS）晶体管的单元电池，其包括集成电路基板和集成电路基板上的MOS晶体管。 MOS晶体管包括源极区，漏极区和栅极。 栅极位于源极区域和漏极区域之间。 在源区和漏区之间提供水平通道。 水平通道包括至少两个间隔开的水平通道区域。 还提供了制造MOS晶体管的相关方法。