公开(公告)号：US20110140277A1

公开(公告)日：2011-06-16

申请号：US13030861

申请日：2011-02-18

申请人： Takashi OKUDA ,  Yasuo Morimoto ,  Yuko Maruyama ,  Toshio Kumamoto

发明人： Takashi OKUDA ,  Yasuo Morimoto ,  Yuko Maruyama ,  Toshio Kumamoto

IPC分类号： H01L23/522

CPC分类号： H01L23/5223 ,  H01L23/5225 ,  H01L2924/0002 ,  H01L2924/3011 ,  H01L2924/00

摘要： A semiconductor device includes a semiconductor substrate including a main surface; a plurality of first interconnections formed in a capacitance forming region defined on the main surface and extending in a predetermined direction; a plurality of second interconnections each adjacent to the first interconnection located at an edge of the capacitance forming region, extending in the predetermined direction, and having a fixed potential; and an insulating layer formed on the main surface and filling in between each of the first interconnections and between the first interconnection and the second interconnection adjacent to each other. The first interconnections and the second interconnections are located at substantially equal intervals in a plane parallel to the main surface, and located to align in a direction substantially perpendicular to the predetermined direction.

摘要翻译： 半导体器件包括：包括主表面的半导体衬底; 多个第一互连形成在形成在主表面上并沿预定方向延伸的电容形成区域中; 多个第二互连，每个相邻于位于电容形成区域的边缘处的第一互连，沿预定方向延伸并具有固定电位; 以及绝缘层，形成在主表面上，并且填充在每个第一互连之间以及第一互连和第二互连之间相邻。 第一互连和第二互连在平行于主表面的平面中以基本相等的间隔定位，并且被定位成在基本上垂直于预定方向的方向上对齐。

公开(公告)号：US07202754B2

公开(公告)日：2007-04-10

申请号：US11280410

申请日：2005-11-17

申请人： Hiroshi Komurasaki ,  Tomohiro Sano ,  Hisayasu Sato ,  Toshio Kumamoto ,  Yasushi Hashizume

发明人： Hiroshi Komurasaki ,  Tomohiro Sano ,  Hisayasu Sato ,  Toshio Kumamoto ,  Yasushi Hashizume

IPC分类号： H03B5/18

CPC分类号： H03B5/1847 ,  H03B5/1215 ,  H03B5/1228 ,  H03B5/1243 ,  H03B5/1256 ,  H03B5/1265 ,  H03B5/1268

摘要： An oscillator circuit is formed of a differential LC resonant circuit formed of an L load differential circuit including inductance-variable portions and a capacitive element, and a positive feedback circuit formed of N-channel MOS transistors. The inductance-variable portion is configured to vary the inductance by selecting a plurality of switch circuits arranged between a plurality of arbitrary positions on a spiral interconnection layer and the input/output terminal, and thereby can control an oscillation frequency. The inductance-variable portions form an inductor pair when the switch circuit among the switch circuits coupled between the first input/output terminals is turned on together with the switch circuit.

摘要翻译： 振荡电路由包括电感可变部分和电容元件的L负载差分电路和由N沟道MOS晶体管形成的正反馈电路构成的差分LC谐振电路形成。 电感可变部被配置为通过选择布置在螺旋互连层上的多个任意位置和输入/输出端之间的多个开关电路来改变电感，从而可以控制振荡频率。 当耦合在第一输入/输出端子之间的开关电路之间的开关电路与开关电路一起导通时，电感可变部分形成电感器对。

公开(公告)号：US07009539B2

公开(公告)日：2006-03-07

申请号：US10715456

申请日：2003-11-19

申请人： Takashi Okuda ,  Toshio Kumamoto ,  Yasuo Morimoto

发明人： Takashi Okuda ,  Toshio Kumamoto ,  Yasuo Morimoto

IPC分类号： H03M3/00

CPC分类号： H03M3/46 ,  H03M3/418 ,  H03M3/454 ,  H03M3/50 ,  H03M7/3022 ,  H03M7/3028 ,  H03M7/304

摘要： A ΔΣ modulator modulates only an error component separated by a component separating portion. Therefore, even if the number of order of the ΔΣ modulator increases, an amplitude of an output of an integrator in the final stage does not excessively increase, and the stability of the modulator can be achieved. Since the signal component separated by the component separating portion does not pass through the ΔΣ modulator, an intensity of an input signal can be maintained as it is, and the modulator can have high precision.

摘要翻译： DeltaSigma调制器仅调制由分量分离部分分离的误差分量。 因此，即使DeltaSigma调制器的次数增加，最终级的积分器的输出的幅度也不会过度增加，并且可以实现调制器的稳定性。 由于由分量分离部分分离的信号分量不通过ΔΣ调制器，所以可以保持输入信号的强度，并且调制器可以具有高精度。

公开(公告)号：US06069579A

公开(公告)日：2000-05-30

申请号：US131238

申请日：1998-08-07

申请人： Masao Ito ,  Takeshi Shigenobu ,  Toshio Kumamoto ,  Takahiro Miki ,  Hiroshi Komurasaki

发明人： Masao Ito ,  Takeshi Shigenobu ,  Toshio Kumamoto ,  Takahiro Miki ,  Hiroshi Komurasaki

IPC分类号： H03M1/14 ,  H03M1/20 ,  H03M1/36 ,  H03M1/12

CPC分类号： H03M1/205 ,  H03M1/141

摘要： An A/D converter simplifies its circuit configuration without deteriorating accuracy in A/D conversion. A circuit is formed of a folding and interpolation type. A gain-variable pre-amplifier group 11 amplifies each of reference voltages Vref1 to VrefN and an analog input voltage Vin, to output the result to a folding amplifier group 12, while a gain-variable pre-amplifier group 21 amplifies each of reference voltages Vrr1 to VrrJ and the analog input voltage Vin, to output the result to a comparator group 24. Each of pre-amplifiers constituting the gain-variable pre-amplifier groups 11 and 21 has an amplification factor that varies in upper and lower comparison periods according to a clock control signal .PHI.cnt.

摘要翻译： A / D转换器简化了其电路配置，而不会降低A / D转换的精度。 电路由折叠和内插形式组成。 增益可变前置放大器组11放大每个参考电压Vref1至VrefN和模拟输入电压Vin，以将结果输出到折叠放大器组12，而增益可变的前置放大器组21放大每个参考电压 Vrr1至VrrJ和模拟输入电压Vin，将结果输出到比较器组24.构成增益可变前置放大器组11和21的每个前置放大器具有在上和下比较周期内变化的放大系数， 到时钟控制信号PHI cnt。

公开(公告)号：US5966088A

公开(公告)日：1999-10-12

申请号：US982279

申请日：1997-12-01

申请人： Osamu Matsumoto ,  Toshio Kumamoto

发明人： Osamu Matsumoto ,  Toshio Kumamoto

IPC分类号： H03M1/44 ,  H03M1/10 ,  H03M1/16

CPC分类号： H03M1/1023 ,  H03M1/168

摘要： An A/D converter includes a sample-hold circuit, A/D converting stages connected in series to the sample-hold circuit, and an encoder/latch circuit which adds 3-bit digital signals issued from the A/D converting stages to each other for outputting a signal of 9 bits. The sample-hold circuit and the A/D converting stages each include a differential amplifier. Differential outputs of each differential amplifier are short-circuited for a predetermined initial period in each sampling period.

摘要翻译： A / D转换器包括采样保持电路，与采样保持电路串联连接的A / D转换级，以及编码器/锁存电路，其将从A / D转换级发出的3位数字信号加到每个 另一个用于输出9位的信号。 采样保持电路和A / D转换级各自包括差分放大器。 在每个采样周期中，每个差分放大器的差分输出在预定的初始周期短路。

公开(公告)号：US5696511A

公开(公告)日：1997-12-09

申请号：US738585

申请日：1996-10-29

申请人： Osamu Matsumoto ,  Toshio Kumamoto

发明人： Osamu Matsumoto ,  Toshio Kumamoto

IPC分类号： H03M1/10 ,  H03F3/45 ,  H03M1/06 ,  H03M1/12 ,  H03M1/14 ,  H03M1/16 ,  H03M1/42

CPC分类号： H03M1/0695 ,  H03M1/167

摘要： In a pipeline type A/D converter, a sample/hold.cndot.subtracter circuit of an A/D converter block of a first stage samples an analog voltage and outputs an offset voltage at a first phase, and subtracts an output voltage of an A/D converter from the sampled analog voltage in a second phase. An A/D converter of an A/D converter block of a succeeding stage subtracts the output voltage of the sample/hold.cndot.subtracter circuit of the first phase from the output voltage of the sample hold.cndot.subtracter circuit of the second phase, and converts the subtracted result into a digital code. The influence of an offset of a differential amplifier included in the sample/hold.cndot.subtracter circuit is removed so that A/D conversion of high accuracy is allowed.

摘要翻译： 在流水线型A / D转换器中，第一级的A / D转换器模块的采样/保持减法器电路对模拟电压进行采样，并在第一阶段输出偏移电压，并且减去A / D转换器从第二阶段的采样模拟电压。 后级的A / D转换器模块的A / D转换器从第二相的采样保持电路的输出电压中减去第一相的采样/保持电路的输出电压，并将其转换 减去结果成数字代码。 除去包含在采样/保持抑制电路中的差分放大器的偏移的影响，使得允许高精度的A / D转换。

公开(公告)号：US5625308A

公开(公告)日：1997-04-29

申请号：US557556

申请日：1995-11-14

申请人： Osamu Matsumoto ,  Takahiro Miki ,  Toshio Kumamoto

发明人： Osamu Matsumoto ,  Takahiro Miki ,  Toshio Kumamoto

IPC分类号： H03M1/34 ,  H03K3/0233 ,  H03K3/356 ,  H03K3/289

CPC分类号： H03K3/35606 ,  H03K3/356034 ,  H03K3/35613

摘要： A high-performance differential latch circuit which includes a differential amplifier circuit comprised of an NMOS transistor (27) serving as a constant current source, PMOS transistors (3, 4) and NMOS transistors (23,24), a latch circuit comprised of NMOS transistors (25, 26), and a switch circuit comprised of NMOS transistors (21,22,28) for alternately operating the differential amplifying function and latch function, the transistor (27) serving as the constant current source having a drain terminal directly connected to the transistors (23,24) and a source terminal directly connected to a ground voltage (2), whereby the differential latch circuit differentially amplifies the signals without the loss of the constant current source function during the differential amplification.

摘要翻译： 一种高性能差分锁存电路，包括由用作恒流源的NMOS晶体管（27），PMOS晶体管（3,4）和NMOS晶体管（23,24）组成的差分放大器电路，由NMOS 晶体管（25,26）以及由NMOS晶体管（21,22,28）组成的用于交替操作差分放大功能和锁存功能的开关电路，用作恒流源的晶体管（27）具有直接连接的漏极端子 到晶体管（23,24）和直接连接到接地电压（2）的源极端子，由此差分锁存电路在差分放大期间不损失恒定电流源功能而差分放大信号。

公开(公告)号：US5539406A

公开(公告)日：1996-07-23

申请号：US264676

申请日：1994-06-23

申请人： Hiroyuki Kouno ,  Toshio Kumamoto ,  Takahiro Miki

发明人： Hiroyuki Kouno ,  Toshio Kumamoto ,  Takahiro Miki

IPC分类号： H03M1/06 ,  H03M1/14 ,  H03M1/36 ,  H03M1/76 ,  H03M1/12

CPC分类号： H03M1/146 ,  H03M1/0682 ,  H03M1/365 ,  H03M1/765

摘要： An upper comparator group compares an analog signal with upper reference potentials applied from upper ladder resistance network. A switch group outputs the predetermined intermediate reference potential of the ladder resistance network to an analog subtracting circuit in response to the upper comparison results. The analog subtracting circuit subtracts the intermediate reference potential from the analog signal for producing an input signal for use in the lower side. A lower ladder resistance network outputs lower reference potentials obtained by dividing by resistors constant static intermediate reference potentials of the ladder resistance network applied from a differential amplifying circuit. A lower comparator group compares the lower reference potentials with the input signal for lower comparison. The upper and the lower comparison results are converted into a digital signal by upper and the lower encoders and the adding/subtracting circuit.

摘要翻译： 上比较器组将模拟信号与上梯形电阻网络施加的较高参考电位进行比较。 开关组响应于较高的比较结果将梯形电阻网络的预定中间参考电位输出到模拟减法电路。 模拟减法电路从用于产生用于下侧的输入信号的模拟信号中减去中间参考电位。 下梯形电阻网络通过将电阻除以由差分放大电路施加的梯形电阻网络的恒定静态中间参考电位而得到的较低参考电位。 较低的比较器组将较低的参考电位与输入信号进行比较，用于较低的比较。 上下比较结果由上下编码器和加减电路转换成数字信号。

公开(公告)号：US5317312A

公开(公告)日：1994-05-31

申请号：US990488

申请日：1992-12-14

申请人： Hiroyuki Kouno ,  Minobu Yazawa ,  Toshio Kumamoto

发明人： Hiroyuki Kouno ,  Minobu Yazawa ,  Toshio Kumamoto

IPC分类号： H03M1/34 ,  H03M1/36

CPC分类号： H03M1/365

摘要： An A/D converter main body is formed in the form of an annulus with a wiring region set as its center, and a ladder resistor array for dividing an input reference voltage and an analog signal line for applying an input analog signal to each comparator in the A/D converter are formed in the form of an annulus with the wiring region set as a center. Wirings from terminals are once concentrated into the wiring region by an input/output line group and then distributed therefrom to circuit elements. Since the ladder resistor array is formed in a circular form, resistance values are less liable to change as compared to the case where the ladder resistor array is bent, resulting in a higher precision of reference voltages for comparison. Further, wiring lengths for control signals to be applied to the circuit elements are made equal, and there is no fear of line delays in the control signals.

摘要翻译： A / D转换器主体形成为以布线区域为中心的环形的形式，以及用于分割输入参考电压的梯形电阻阵列和用于将输入的模拟信号施加到每个比较器的模拟信号线 A / D转换器形成为以布线区域为中心的环形的形式。 来自端子的布线一旦通过输入/输出线组集中到布线区域中，然后从电缆元件分布。 由于梯形电阻器阵列形成为圆形形式，所以与梯形电阻器阵列弯曲的情况相比，电阻值不易变化，因此比较了较高的基准电压精度。 此外，使施加到电路元件的控制信号的布线长度相等，并且不必担心控制信号中的线路延迟。

公开(公告)号：US4827262A

公开(公告)日：1989-05-02

申请号：US76858

申请日：1987-07-23

申请人： Toshio Kumamoto ,  Masao Nakaya

发明人： Toshio Kumamoto ,  Masao Nakaya

IPC分类号： H03M1/36 ,  H03M1/00 ,  H03M1/78

CPC分类号： H03M1/361

摘要： A comparator bank of an A/D converter comprising a plurality of comparators arranged into rows in a folded-back shape and a supply voltage line and a ground line in parallel with each other and connected to the comparators to provide reference potentials thereto according to a distribution shape which rises and falls continuously along the rows of the comparators whereby the linearity of the A/D converter is effectively maintained. The nodes of the comparators do not intersect and are arranged to successively become further from reference points set at the terminals of the supply voltage and ground lines.

摘要翻译： 一种A / D转换器的比较器组，包括多个比较器，其布置成折叠形状的行，并且电源电压线和地线彼此并联连接并连接到比较器，以根据 分布形状沿着比较器的行连续地上升和下降，从而有效地保持A / D转换器的线性。 比较器的节点不相交并且被布置成从设置在电源电压和接地线的端子处的参考点依次变得更远。