公开(公告)号：US20120095715A1

公开(公告)日：2012-04-19

申请号：US12907586

申请日：2010-10-19

申请人： Dipankar Nag ,  Mei-Show Chen ,  Chewn-Pu Jou

发明人： Dipankar Nag ,  Mei-Show Chen ,  Chewn-Pu Jou

IPC分类号： G06F19/00

CPC分类号： H03H11/1291 ,  H03H2011/0494 ,  H03H2210/025 ,  H03H2210/04 ,  H03J2200/08

摘要： A method of calibrating a filter includes applying an input signal into the filter to generate an output signal, measuring a phase difference between the input signal and the output signal; determining a leading/lagging status of the phase difference; calculating a capacitor code (CAP_CODE) using the leading/lagging status; and calibrating the capacitor using the CAP_CODE.

摘要翻译： 校准滤波器的方法包括将输入信号施加到滤波器中以产生输出信号，测量输入信号和输出信号之间的相位差; 确定相位差的前导/滞后状态; 使用前导/滞后状态计算电容代码（CAP_CODE）; 并使用CAP_CODE校准电容器。

公开(公告)号：US09780211B2

公开(公告)日：2017-10-03

申请号：US13731873

申请日：2012-12-31

申请人： Chewn-Pu Jou ,  Tzu-Jin Yeh ,  Chia-Chung Chen

发明人： Chewn-Pu Jou ,  Tzu-Jin Yeh ,  Chia-Chung Chen

IPC分类号： H01L27/088 ,  H01L29/78 ,  H01L29/66

CPC分类号： H01L29/785 ,  H01L29/66901

摘要： A power cell includes a fin over a substrate, the fin extending in a direction substantially perpendicular to a bottom surface of the substrate. The fin includes a first dopant type. The power cell further includes at least one isolation region over the substrate between the fin and an adjacent fin. The power cell further includes a gate structure in contact with the fin and the at least one isolation region, wherein the gate structure comprises a doped region in the fin, wherein the doped region has a second dopant type different from the first dopant type and the doped region defines a channel region in the fin.

公开(公告)号：US09129940B2

公开(公告)日：2015-09-08

申请号：US13419911

申请日：2012-03-14

申请人： Hsieh-Hung Hsieh ,  Yi-Hsuan Liu ,  Tzu-Jin Yeh ,  Chewn-Pu Jou ,  Fu-Lung Hsueh

发明人： Hsieh-Hung Hsieh ,  Yi-Hsuan Liu ,  Tzu-Jin Yeh ,  Chewn-Pu Jou ,  Fu-Lung Hsueh

IPC分类号： G01R35/00 ,  H01L23/48 ,  H01L23/66 ,  H01L25/065 ,  H04B5/00

CPC分类号： H01L23/48 ,  H01L23/66 ,  H01L25/0657 ,  H01L2225/06531 ,  H01L2924/0002 ,  H04B5/0075 ,  H01L2924/00

摘要： An integrated circuit includes a first chip and a second chip coupled to the first chip in a vertical stack. The first chip includes a radio frequency circuit and a first coil electrically coupled to the radio frequency circuit. The second chip includes a calibration circuit and a second coil electrically coupled to the calibration circuit. The calibration circuit is configured to calibrate the radio frequency circuit disposed on the first chip through inductive coupling between the first and second coils.

摘要翻译： 集成电路包括在垂直堆叠中耦合到第一芯片的第一芯片和第二芯片。 第一芯片包括射频电路和电耦合到射频电路的第一线圈。 第二芯片包括校准电路和电耦合到校准电路的第二线圈。 校准电路被配置为通过第一和第二线圈之间的感应耦合来校准设置在第一芯片上的射频电路。

公开(公告)号：US20140049329A1

公开(公告)日：2014-02-20

申请号：US13586033

申请日：2012-08-15

申请人： Yen-Jen Chen ,  I-Ting Lee ,  Hsieh-Hung Hsieh ,  Chewn-Pu Jou ,  Fu-Lung Hsueh ,  Shen-Luan Liu

发明人： Yen-Jen Chen ,  I-Ting Lee ,  Hsieh-Hung Hsieh ,  Chewn-Pu Jou ,  Fu-Lung Hsueh ,  Shen-Luan Liu

IPC分类号： H03L7/099

CPC分类号： H03K3/0322 ,  H03K3/0315 ,  H03L7/083 ,  H03L7/087 ,  H03L7/089 ,  H03L7/099

摘要： One or more techniques and systems for a divider-less phase locked loop (PLL) and associated phase detector (PD) are provided herein. In some embodiments, a pulse phase detector (pulsePD) signal, a voltage controlled oscillator positive differential (VCOP) signal, and a voltage controlled oscillator negative differential (VCON) signal are received. An up signal and a down signal for a first charge pump (CP) and an up signal and a down signal for a second CP are generated based on the pulsePD signal, the VCOP signal, and the VCON signal. For example, CP signals are generated to control the first CP and the second CP, respectively. In some embodiments, CP signals are generated such that the CPs facilitate adjustment of a zero crossing phase of the VCON and VCOP signals with respect to the pulsePD signal. In this manner, a divider-less PLL is provided, thus mitigating PLL power consumption.

摘要翻译： 本文提供了一种用于无分频锁相环（PLL）和相关相位检测器（PD）的技术和系统。 在一些实施例中，接收脉冲相位检测器（pulsePD）信号，压控振荡器正差分（VCOP）信号和压控振荡器负差分（VCON）信号。 基于pulsePD信号，VCOP信号和VCON信号产生用于第一电荷泵（CP）的上升信号和下降信号以及用于第二CP的上升信号和下降信号。 例如，生成CP信号以分别控制第一CP和第二CP。 在一些实施例中，产生CP信号，使得CP有助于调整相对于pulsePD信号的VCON和VCOP信号的零交叉相位。 以这种方式，提供无分频PLL，从而减轻PLL功耗。

公开(公告)号：US08476972B2

公开(公告)日：2013-07-02

申请号：US12813620

申请日：2010-06-11

申请人： You-Jen Wang ,  Shen-Iuan Liu ,  Feng Wei Kuo ,  Chewn-Pu Jou ,  Fu-Lung Hsueh

发明人： You-Jen Wang ,  Shen-Iuan Liu ,  Feng Wei Kuo ,  Chewn-Pu Jou ,  Fu-Lung Hsueh

IPC分类号： G06G7/12 ,  G06G7/26

CPC分类号： G04F10/005

摘要： A time amplifier circuit has first and second inverters and first and second pull-down paths. Each inverter includes a first NMOS transistor and a first PMOS transistor. A source of the first NMOS transistor is coupled to a ground node directly or through a first additional NMOS transistor having a gate coupled to a respective input node. The first and second inverters are coupled to first and second input nodes and to first and second output nodes, respectively. The first pull-down path is from the first output node to the ground node and is enabled in response to the first input signal and the second output signal being high. The second pull-down path is from the second output node to ground and is enabled in response to the second input signal and the first output signal being high.

摘要翻译： 时间放大器电路具有第一和第二反相器以及第一和第二下拉通路。 每个反相器包括第一NMOS晶体管和第一PMOS晶体管。 第一NMOS晶体管的源极直接或通过具有耦合到相应输入节点的栅极的第一附加NMOS晶体管耦合到接地节点。 第一和第二反相器分别耦合到第一和第二输入节点以及第一和第二输出节点。 第一下拉路径从第一输出节点到接地节点，并且响应于第一输入信号而使第二输出信号为高。 第二下拉路径从第二输出节点到地，并且响应于第二输入信号并且第一输出信号为高而使能。

公开(公告)号：US08344720B2

公开(公告)日：2013-01-01

申请号：US12770033

申请日：2010-04-29

申请人： Dipankar Nag ,  Chewn-Pu Jou

发明人： Dipankar Nag ,  Chewn-Pu Jou

IPC分类号： G05F3/16

CPC分类号： G05F3/16 ,  G05F3/30

摘要： A reference voltage generator includes a proportional to absolute temperature (PTAT) current source and a voltage divider. The PTAT current source is capable of providing a first current that is proportional to a temperature. The voltage divider is capable of receiving a second current that is proportional to the first current. The voltage divider is capable of outputting a reference voltage. The reference voltage is substantially independent from a change of the temperature.

摘要翻译： 参考电压发生器包括与绝对温度（PTAT）电流源和分压器成比例的比例。 PTAT电流源能够提供与温度成比例的第一电流。 分压器能够接收与第一电流成比例的第二电流。 分压器能够输出参考电压。 参考电压基本上与温度的变化无关。

公开(公告)号：US08324658B2

公开(公告)日：2012-12-04

申请号：US12759743

申请日：2010-04-14

申请人： Ming-Hsien Tsai ,  Chewn-Pu Jou ,  Fu-Lung Hsueh ,  Ming-Hsiang Song

发明人： Ming-Hsien Tsai ,  Chewn-Pu Jou ,  Fu-Lung Hsueh ,  Ming-Hsiang Song

IPC分类号： H01L29/73

CPC分类号： H01L29/73

摘要： An electrostatic discharge (ESD) protection circuit structure includes a dual directional silicon controlled rectifier (SCR) formed in a substrate. The SCR includes first and second P-wells laterally interposed by an N-well. A deep N-well is disposed underneath the P-wells and the N-well. First and second N-type regions are disposed in the first and second P-wells, respectively, and are coupled to a pair of pads. First and second P-type regions are disposed in the first and second P-wells, respectively, are coupled to the pads, and are disposed closer to the N-well than the first and second N-type regions, respectively.

摘要翻译： 静电放电（ESD）保护电路结构包括形成在衬底中的双向可控硅整流器（SCR）。 SCR包括由N阱横向插入的第一和第二P阱。 深井N井位于P井和N井的下面。 第一和第二N型区域分别设置在第一和第二P阱中，并且耦合到一对焊盘。 第一和第二P型区域分别设置在第一和第二P阱中，分别耦合到焊盘，并且分别设置成比第一和第二N型区域更靠近N阱。

公开(公告)号：US20120286836A1

公开(公告)日：2012-11-15

申请号：US13103571

申请日：2011-05-09

申请人： Hsieh-Hung Hsieh ,  Ming Hsien Tsai ,  Tzu-Jin Yeh ,  Chewn-Pu Jou ,  Fu-Lung Hsueh

发明人： Hsieh-Hung Hsieh ,  Ming Hsien Tsai ,  Tzu-Jin Yeh ,  Chewn-Pu Jou ,  Fu-Lung Hsueh

IPC分类号： H03K3/84

CPC分类号： G01R31/2824

摘要： A built-in self-test circuit for testing a voltage controlled oscillator comprises a voltage controlled oscillator, a buffer having an input coupled to an output of the voltage controlled oscillator and a radio frequency peak detector coupled to the output of the buffer. The radio frequency peak detector is configured to receive an ac signal from the voltage controlled oscillator and generate a dc value proportional to the ac signal at an output of the radio frequency peak detector. Furthermore, the output of the radio frequency peak detector generates a dc value proportional to an amplitude of the ac signal from the voltage controlled oscillator when the voltage controlled oscillator functions correctly. On the other hand, the output of the radio frequency peak detector is at zero volts when the voltage controlled oscillator fails to generate an ac signal.

摘要翻译： 用于测试压控振荡器的内置自检电路包括压控振荡器，具有耦合到压控振荡器的输出的输入的缓冲器和耦合到缓冲器的输出的射频峰值检测器。 射频峰值检测器被配置为从压控振荡器接收交流信号，并且在射频峰值检测器的输出处产生与ac信号成比例的直流值。 此外，当压控振荡器正常工作时，射频峰值检测器的输出产生与来自压控振荡器的ac信号的幅度成比例的直流值。 另一方面，当压控振荡器不能产生交流信号时，射频峰值检测器的输出为零伏特。

公开(公告)号：US09490248B2

公开(公告)日：2016-11-08

申请号：US13753995

申请日：2013-01-30

申请人： Tzu-Jin Yeh ,  Chewn-Pu Jou ,  Jun-De Jin

发明人： Tzu-Jin Yeh ,  Chewn-Pu Jou ,  Jun-De Jin

IPC分类号： H01L29/66 ,  H01L29/772 ,  H01L27/06 ,  H03K17/10 ,  H01L29/78 ,  H01L29/06 ,  H01L29/10

CPC分类号： H01L27/0629 ,  H01L29/0653 ,  H01L29/1087 ,  H01L29/66484 ,  H01L29/66636 ,  H01L29/7832 ,  H03K17/102 ,  H03K2217/0018

摘要： A power cell including an isolation region having a first dopant type formed in a substrate. The power cell further includes a bottom gate having a second dopant type different from the first dopant type formed on the isolation region and a channel layer having the first dopant type formed on the bottom gate. The power cell further includes source/drain regions having the first dopant type formed in the channel layer and a first well region having the second dopant type formed around the channel layer and the source/drain regions, and the first well region electrically connected to the bottom gate. The power cell further includes a second well region having the first dopant type formed around the channel layer and contacting the isolation region and a gate structure formed on the channel layer.

摘要翻译： 一种功率单元，包括形成在基板中的具有第一掺杂剂类型的隔离区域。 功率单元还包括具有不同于在隔离区上形成的第一掺杂剂类型的第二掺杂剂型的底栅和在底栅上形成的具有第一掺杂剂类型的沟道层。 功率单元还包括在沟道层中形成的具有第一掺杂剂类型的源极/漏极区域和形成在沟道层和源极/漏极区域周围的具有第二掺杂剂类型的第一阱区域，以及与第一阱区域电连接的第一阱区域 底门 功率单元还包括具有第一掺杂剂类型的第二阱区，该第二阱区形成在沟道层周围并与隔离区接触并形成在沟道层上的栅极结构。

公开(公告)号：US09275923B2

公开(公告)日：2016-03-01

申请号：US13557457

申请日：2012-07-25

申请人： Feng Wei Kuo ,  Huan-Neng Chen ,  Chewn-Pu Jou ,  Shuo-Mao Chen ,  Der-Chyang Yeh

发明人： Feng Wei Kuo ,  Huan-Neng Chen ,  Chewn-Pu Jou ,  Shuo-Mao Chen ,  Der-Chyang Yeh

IPC分类号： H05K7/00 ,  H01L21/56 ,  H01L23/31 ,  H01L23/64 ,  H01L23/66 ,  H01L25/16 ,  H01L23/00

CPC分类号： H01L23/3128 ,  H01L23/642 ,  H01L23/66 ,  H01L24/24 ,  H01L24/82 ,  H01L25/16 ,  H01L2223/6627 ,  H01L2223/6672 ,  H01L2224/12105 ,  H01L2224/24195 ,  H01L2924/181 ,  H01L2924/19011 ,  H01L2924/00

摘要： Some embodiments relate to a device and method for a band pass filter with a reduced cost, area penalty, and manufacturing complexity relative to current solutions. An integrated passive device chip includes a plurality of capacitors embedded in a common molding compound along with a transceiver chip. The integrated passive device chip and the transceiver chip are also arranged within a polymer package. An ultra-thick metallization layer is disposed within the polymer package and configured to couple the integrated passive device chip to the transceiver chip. The ultra-thick metallization layer also forms a plurality of transmission lines, wherein the combined integrated passive device chip and transmission lines form a band pass filter with improved frequency response, noise immunity, and cost and area as compared to conventional solutions.

摘要翻译： 一些实施例涉及一种带通滤波器的器件和方法，其具有相对于当前解决方案的降低的成本，面积损失和制造复杂性。 集成的无源器件芯片包括嵌入在共同的模制化合物中的多个电容器以及收发器芯片。 集成无源器件芯片和收发器芯片也布置在聚合物封装内。 超厚金属化层设置在聚合物封装内并且被配置成将集成的无源器件芯片耦合到收发器芯片。 超厚金属化层还形成多条传输线，其中与常规解决方案相比，组合的集成无源器件芯片和传输线形成具有改进的频率响应，抗噪声性以及成本和面积的带通滤波器。