公开(公告)号：US11728290B2

公开(公告)日：2023-08-15

申请号：US16394514

申请日：2019-04-25

Applicant: Intel Corporation

Inventor： Adel A. Elsherbini ,  Georgios Dogiamis ,  Johanna M. Swan ,  Aleksandar Aleksov ,  Telesphor Kamgaing ,  Henning Braunisch

IPC: H01L23/66 ,  H01L23/538 ,  H01L25/065 ,  H01L23/00 ,  H01L21/48 ,  H01L21/683 ,  H01L25/00

CPC classification number: H01L23/66 ,  H01L21/486 ,  H01L21/4857 ,  H01L21/6835 ,  H01L23/5386 ,  H01L24/16 ,  H01L25/0655 ,  H01L25/50 ,  H01L24/97 ,  H01L2221/68345 ,  H01L2221/68359 ,  H01L2223/6616 ,  H01L2223/6627 ,  H01L2223/6683 ,  H01L2224/16227 ,  H01L2924/1423 ,  H01L2924/1903

Abstract: Embodiments may relate to a microelectronic package that includes a substrate signal path and a waveguide. The package may further include dies that are communicatively coupled with one another by the substrate signal path and the waveguide. The substrate signal path may carry a signal with a frequency that is different than the frequency of a signal that is to be carried by the waveguide. Other embodiments may be described or claimed.

公开(公告)号：US11721649B2

公开(公告)日：2023-08-08

申请号：US17748877

申请日：2022-05-19

Applicant: Intel Corporation

Inventor： Adel A. Elsherbini ,  Patrick Morrow ,  Henning Braunisch ,  Kimin Jun ,  Brennen Mueller ,  Shawna M. Liff ,  Johanna M. Swan ,  Paul B. Fischer

IPC: H01L23/66 ,  H01L23/64 ,  H01L23/36 ,  H01L23/49 ,  H01L23/538 ,  H01L23/34 ,  H01L49/02

CPC classification number: H01L23/645 ,  H01L23/34 ,  H01L23/66 ,  H01L28/10 ,  H01L2223/6677

Abstract: Microelectronic assemblies, and related devices and methods, are disclosed herein. For example, in some embodiments, a microelectronic assembly may include a die having a front side and a back side, the die comprising a first material and conductive contacts at the front side; and a thermal layer attached to the back side of the die, the thermal layer comprising a second material and a conductive pathway, wherein the conductive pathway extends from a front side of the thermal layer to a back side of the thermal layer.

公开(公告)号：US11716826B2

公开(公告)日：2023-08-01

申请号：US16402055

申请日：2019-05-02

Applicant: Intel Corporation

Inventor： Telesphor Kamgaing ,  Johanna M. Swan ,  Georgios Dogiamis ,  Henning Braunisch ,  Adel A. Elsherbini ,  Aleksandar Aleksov ,  Richard Dischler

IPC: H05K7/14 ,  H05K1/02 ,  H01P5/12 ,  H01P3/16 ,  H01L23/00 ,  H01L25/18 ,  H01L23/66 ,  H01L23/538 ,  H05K1/18

CPC classification number: H05K7/1489 ,  H01P3/16 ,  H01P5/12 ,  H05K1/0243 ,  H01L23/5384 ,  H01L23/5386 ,  H01L23/66 ,  H01L24/16 ,  H01L25/18 ,  H01L2223/6616 ,  H01L2223/6627 ,  H01L2224/16225 ,  H05K1/181 ,  H05K2201/10356 ,  H05K2201/10378 ,  H05K2201/10734

Abstract: Embodiments may relate an electronic device that includes a first platform and a second platform coupled with a chassis. The platforms may include respective microelectronic packages. The electronic device may further include a waveguide coupled to the first platform and the second platform such that their respective microelectronic packages are communicatively coupled by the waveguide. Other embodiments may be described or claimed.

公开(公告)号：US11664303B2

公开(公告)日：2023-05-30

申请号：US17375360

申请日：2021-07-14

Applicant: Intel Corporation

Inventor： Johanna Swan ,  Henning Braunisch ,  Aleksandar Aleksov ,  Shawna Liff ,  Brandon Rawlings ,  Veronica Strong

IPC: H01L23/498 ,  G03F1/38 ,  G03F1/54 ,  G03F1/68

CPC classification number: H01L23/49838 ,  G03F1/38 ,  G03F1/54 ,  G03F1/68 ,  H01L23/49827 ,  H01L23/49866

Abstract: An lithographic reticle may be formed comprising a transparent substrate, a substantially opaque mask formed on the transparent substrate that defines at least one exposure window, wherein the at least one exposure window has a first end, a first filter formed on the transparent substrate within the at least one exposure window and abutting the first end thereof, and a second filter formed on the transparent substrate within the at least one exposure window and abutting the first filter, wherein an average transmissivity of the first filter is substantially one half of a transmissivity of the second filter. In another embodiment, the at least one exposure window includes a third filter abutting the second end and is adjacent the second filter. Further embodiments of the present description include interconnection structures and systems fabricated using the lithographic reticle.

公开(公告)号：US20230098020A1

公开(公告)日：2023-03-30

申请号：US17484384

申请日：2021-09-24

Applicant: Intel Corporation

Inventor： Feras Eid ,  Aleksandar Aleksov ,  Henning Braunisch ,  Adel Elsherbini ,  Thomas L. Sounart ,  Johanna Swan

IPC: H01L23/473 ,  H01L23/50 ,  H05K7/20 ,  H01L23/31

Abstract: Technologies for cooling conformal power delivery structures are disclosed. In one embodiment, an integrated circuit component has a die with a backside power plane mated to it. A lid of the integrated circuit component is mated with the backside power plane, forming a sealed cavity. The lid has an inlet and an outlet, and a channel is defined in the lid for liquid coolant to flow from the inlet, across the backside power plane, and to the outlet. The liquid coolant directly contacts the backside power plane, efficiently removing heat from the backside power plane.

公开(公告)号：US20230095654A1

公开(公告)日：2023-03-30

申请号：US17484213

申请日：2021-09-24

Applicant: Intel Corporation

Inventor： Adel Elsherbini ,  Feras Eid ,  Stephen Morein ,  Krishna Bharath ,  Henning Braunisch ,  Beomseok Choi ,  Brandon M. Rawlings ,  Thomas L. Sounart ,  Johanna Swan ,  Yoshihiro Tomita ,  Aleksandar Aleksov

IPC: H01L23/498 ,  H01L23/48 ,  H01L25/065 ,  H01L21/48

Abstract: In one embodiment, a conformal power delivery structure includes a first electrically conductive layer comprising metal. The first electrically conductive layer defines one or more recesses, and the conformal power delivery structure also includes a second electrically conductive layer comprising metal that is at least partially within the recesses of the first electrically conductive layer. The second electrically conductive layer has a lower surface that generally conforms with the upper surface of the first electrically conductive layer. The conformal power delivery structure further includes a dielectric material between the surfaces of the first electrically conductive layer and the second electrically conductive layer that conform with one another.

公开(公告)号：US11460499B2

公开(公告)日：2022-10-04

申请号：US16573946

申请日：2019-09-17

Applicant: Intel Corporation

Inventor： Henning Braunisch ,  Aleksandar Aleksov ,  Veronica Strong ,  Brandon Rawlings ,  Johanna Swan ,  Shawna Liff

IPC: H01L23/498 ,  H01L23/538 ,  H01L23/31 ,  G01R31/28 ,  G01K7/42 ,  G01K7/02

Abstract: An integrated circuit package having an electronic interposer comprising an upper section, a lower section and a middle section, a die side integrated circuit device electrically attached to the upper section of the electronic interposer, a die side heat dissipation device thermally contacting the die side integrated circuit device, a land side integrated circuit device electrically attached to the lower section of the electronic interposer, and a land side heat dissipation device thermally contacting the at least one die side integrated circuit device. The upper section and the lower section may each have between two and four layers and the middle section may be formed between the upper section and the lower section, and comprises up to eight layers, wherein a thickness of each layer of the middle section is thinner than a thickness of any of the layers of the upper section and the lower section.

公开(公告)号：US20220278057A1

公开(公告)日：2022-09-01

申请号：US17748877

申请日：2022-05-19

Applicant: Intel Corporation

Inventor： Adel A. Elsherbini ,  Patrick Morrow ,  Henning Braunisch ,  Kimin Jun ,  Brennen Karl Mueller ,  Shawna M. Liff ,  Johanna M. Swan ,  Paul B. Fischer

IPC: H01L23/64 ,  H01L23/34 ,  H01L23/66 ,  H01L49/02

Abstract: Microelectronic assemblies, and related devices and methods, are disclosed herein. For example, in some embodiments, a microelectronic assembly may a die having a front side and a back side, the die comprising a first material and conductive contacts at the front side; and a thermal layer attached to the back side of the die, the thermal layer comprising a second material and a conductive pathway, wherein the conductive pathway extends from a front side of the thermal layer to a back side of the thermal layer.

公开(公告)号：US11329359B2

公开(公告)日：2022-05-10

申请号：US16014036

申请日：2018-06-21

Applicant: Intel Corporation

Inventor： Georgios Dogiamis ,  Adel A. Elsherbini ,  Telesphor Kamgaing ,  Henning Braunisch ,  Johanna M. Swan

IPC: H01P3/16 ,  H01L23/66 ,  H01P11/00 ,  H04B10/2581

Abstract: Disclosed herein are various designs for dielectric waveguides, as well as methods of manufacturing such waveguides. One type of dielectric waveguides described herein includes waveguides with one or more cavities in the dielectric waveguide material. Another type of dielectric waveguides described herein includes waveguides with a conductive ridge in the dielectric waveguide material. Dielectric waveguides described herein may be dispersion reduced dielectric waveguides, compared to conventional dielectric waveguides, and may be designed to adjust the difference in the group delay between the lower frequencies and the higher frequencies of a chosen bandwidth.

公开(公告)号：US11329358B2

公开(公告)日：2022-05-10

申请号：US16841072

申请日：2020-04-06

Applicant: Intel Corporation

Inventor： Adel A. Elsherbini ,  Mathew Manusharow ,  Krishna Bharath ,  Zhichao Zhang ,  Yidnekachew S. Mekonnen ,  Aleksandar Aleksov ,  Henning Braunisch ,  Feras Eid ,  Javier Soto

IPC: H01P3/08 ,  H01P3/02 ,  H05K1/02 ,  H01P3/06

Abstract: Embodiments of the invention include a packaged device with transmission lines that have an extended thickness, and methods of making such device. According to an embodiment, the packaged device may include a first dielectric layer and a first transmission line formed over the first dielectric layer. Embodiments may then include a second dielectric layer formed over the transmission line and the first dielectric layer. According to an embodiment, a first line via may be formed through the second dielectric layer and electrically coupled to the first transmission line. In some embodiments, the first line via extends substantially along the length of the first transmission line.