公开(公告)号：US20200286685A1

公开(公告)日：2020-09-10

申请号：US16294811

申请日：2019-03-06

Applicant: Intel Corporation

Inventor： Chia-Ching Lin ,  Sou-Chi Chang ,  Ashish Verma Penumatcha ,  Nazila Haratipour ,  Seung Hoon Sung ,  Owen Y. Loh ,  Jack Kavalieros ,  Uygar E. Avci ,  Ian A. Young

IPC: H01G7/06 ,  H01L49/02 ,  H01L27/108

Abstract: Described is a ferroelectric based capacitor that reduces non-polar monoclinic phase and increases polar orthorhombic phase by epitaxial strain engineering in the oxide thin film and/or electrodes. As such, both memory window and reliability are improved. The capacitor comprises: a first structure comprising metal, wherein the first structure has a first lattice constant; a second structure comprising metal, wherein the second structure has a second lattice constant; and a third structure comprising ferroelectric material (e.g., oxide of Hf or Zr), wherein the third structure is between and adjacent to the first and second structures, wherein the third structure has a third lattice constant, and wherein the first and second lattice constants are smaller than the third lattice constant.

公开(公告)号：US20240114696A1

公开(公告)日：2024-04-04

申请号：US17957603

申请日：2022-09-30

Applicant: Intel Corporation

Inventor： Christopher Neumann ,  Cory Weinstein ,  Nazila Haratipour ,  Brian Doyle ,  Sou-Chi Chang ,  Tristan Tronic ,  Shriram Shivaraman ,  Uygar Avci

IPC: H01L27/11507 ,  H01L27/11514

CPC classification number: H01L27/11507 ,  H01L27/11514

Abstract: Multiple-ferroelectric capacitor structures in memory devices, including in integrated circuit devices, and techniques for forming the structures. Insulators separating individual outer plates in a ferroelectric capacitor array are supported between wider portions of a shared, inner plate. Wider portions of an inner plate may be formed in lateral recesses between insulating layers. Ferroelectric material may be deposited over the inner plate between insulating layers after removing sacrificial layers. An etch-stop layer may protect the inner plate when sacrificial layers are removed. An etch-stop or interface layer may remain over the inner plate adjacent insulators.

公开(公告)号：US20240114694A1

公开(公告)日：2024-04-04

申请号：US17937043

申请日：2022-09-30

Applicant: Intel Corporation

Inventor： Sourav Dutta ,  Nazila Haratipour ,  Uygar E. Avci ,  Vachan Kumar ,  Christopher M. Neumann ,  Shriram Shivaraman ,  Sou-Chi Chang ,  Brian S. Doyle

IPC: H01L27/11507

CPC classification number: H01L27/11507

Abstract: Backside integrated circuit capacitor structures. In an example, a capacitor structure includes a layer of ferroelectric material between first and second electrodes. The first electrode can be connected to a transistor terminal by a backside contact that extends downward from a bottom surface of the transistor terminal to the first electrode. The transistor terminal can be, for instance, a source or drain region, and the backside contact can be self-aligned with the source or drain region. The second electrode can be connected to a backside interconnect feature. In some cases, the capacitor has a height that extends through at least one backside interconnect layer. In some cases, the capacitor is a multi-plate capacitor in which the second conductor is one of a plurality of plate line conductors arranged in a staircase structure. The capacitor structure may be, for example, part of a non-volatile memory device or the cache of a processor.

公开(公告)号：US20240114692A1

公开(公告)日：2024-04-04

申请号：US17958395

申请日：2022-10-01

Applicant: Intel Corporation

Inventor： Nazila Haratipour ,  Uygar E. Avci ,  Vachan Kumar ,  Hai Li ,  Yu-Ching Liao ,  Ian Alexander Young

IPC: H01L27/11502 ,  G11C11/22 ,  H01L27/108 ,  H01L29/94

CPC classification number: H01L27/11502 ,  G11C11/221 ,  G11C11/223 ,  H01L27/1087 ,  H01L29/945

Abstract: Inverted pillar capacitors that have a U-shaped insulating layer are oriented with the U-shaped opening of the insulating layer opening toward the surface of the substrate on which the inverted pillar capacitors are formed. The bottom electrodes of adjacent inverted pillar capacitors are isolated from each other by the insulating layers of the adjacent electrodes and the top electrode that fills the volume between the electrodes. By avoiding the need to isolate adjacent bottom electrodes by an isolation dielectric region, inverted pillar capacitors can provide for a greater capacitor density relative to non-inverted pillar capacitors. The insulating layer in inverted pillar capacitors can comprise a ferroelectric material or an antiferroelectric material. The inverted pillar capacitor can be used in memory circuits (e.g., DRAMs) or non-memory applications.

公开(公告)号：US20240113101A1

公开(公告)日：2024-04-04

申请号：US17936990

申请日：2022-09-30

Applicant: Intel Corporation

Inventor： Sourav Dutta ,  Nazila Haratipour ,  Vachan Kumar ,  Uygar E. Avci ,  Shriram Shivaraman ,  Sou-Chi Chang

IPC: H01L27/06 ,  H01L29/08 ,  H01L29/40 ,  H01L29/417 ,  H01L29/423 ,  H01L29/66 ,  H01L29/778 ,  H01L49/02

CPC classification number: H01L27/0629 ,  H01L28/55 ,  H01L29/0847 ,  H01L29/401 ,  H01L29/41733 ,  H01L29/42392 ,  H01L29/66545 ,  H01L29/778 ,  H01L29/0673

Abstract: Techniques are provided herein to form a semiconductor device that has a capacitor structure integrated with the source or drain region of the semiconductor device. A given semiconductor device includes one or more semiconductor regions extending in a first direction between corresponding source or drain regions. A gate structure extends in a second direction over the one or more semiconductor regions. A capacitor structure is integrated with one of the source or drain regions of the integrated circuit such that a first electrode of the capacitor contacts the source or drain region and a second electrode of the capacitor contacts a conductive contact formed over the capacitor structure. The capacitor structure may include a ferroelectric capacitor having a ferroelectric layer between the electrodes.

公开(公告)号：US20240112730A1

公开(公告)日：2024-04-04

申请号：US17957945

申请日：2022-09-30

Applicant: Intel Corporation

Inventor： Sou-Chi Chang ,  Nazila Haratipour ,  Saima Siddiqui ,  Uygar Avci ,  Chia-Ching Lin

IPC: G11C13/00 ,  G11C11/22 ,  H01L45/00

CPC classification number: G11C13/0026 ,  G11C11/22 ,  G11C13/0007 ,  G11C13/0028 ,  G11C13/0033 ,  G11C13/004 ,  G11C13/0069 ,  H01L45/1233 ,  H01L45/1253 ,  H01L45/146 ,  G11C2213/79

Abstract: Techniques and mechanisms for storing data with a memory cell which comprises a ferroelectric (FE) resistive junction. In an embodiment, a memory cell comprises a transistor and a FE resistive junction structure which is coupled to the transistor. The FE resistive junction structure comprises electrode structures, and a layer of a material which is between said electrode structures, wherein the material is a FE oxide or a FE semiconductor. The FE resistive junction structure selectively provides any of various levels of resistance, each to represent a respective one or more bits. A current flow through the FE resistive junction structure is characterized by thermionic emission through a Schottky barrier at an interface with one of the electrode structures. In another embodiment, the FE resistive junction structure further comprises one or more dielectric layers each between the layer of material and a different respective one of the electrode structures.

公开(公告)号：US20240105508A1

公开(公告)日：2024-03-28

申请号：US17935647

申请日：2022-09-27

Applicant: Intel Corporation

Inventor： Jitendra Kumar Jha ,  Justin Mueller ,  Nazila Haratipour ,  Gilbert W. Dewey ,  Chi-Hing Choi ,  Jack T. Kavalieros ,  Siddharth Chouksey ,  Nancy Zelick ,  Jean-Philippe Turmaud ,  I-Cheng Tung ,  Blake Bluestein

IPC: H01L21/768 ,  H01L29/49

CPC classification number: H01L21/76856 ,  H01L21/76837 ,  H01L21/76877 ,  H01L29/4908

Abstract: Disclosed herein are integrated circuit (IC) devices with contacts using nitridized molybdenum. For example, a contact arrangement for an IC device may include a semiconductor material and a contact extending into a portion of the semiconductor material. The contact may include molybdenum. The molybdenum may be in a first layer and a second layer, where the second layer may further include nitrogen. The first layer may have a thickness between about 5 nanometers and 16 nanometers, and the second layer may have a thickness between about 0.5 nanometers to 2.5 nanometers. The contact may further include a fill material (e.g., an electrically conductive material) and the second layer may be in contact with the fill material. The molybdenum may have a low resistance, and thus may improve the electrical performance of the contact. The nitridized molybdenum may prevent oxidation during the fabrication of the contact.

公开(公告)号：US20240006533A1

公开(公告)日：2024-01-04

申请号：US17856982

申请日：2022-07-02

Applicant: Intel Corporation

Inventor： Gilbert Dewey ,  Siddharth Chouksey ,  Nazila Haratipour ,  Christopher Jezewski ,  Jitendra Kumar Jha ,  Ilya V. Karpov ,  Matthew V. Metz ,  Arnab Sen Gupta ,  I-Cheng Tung ,  Nancy Zelick ,  Chi-Hing Choi ,  Dan S. Lavric

IPC: H01L29/78 ,  H01L29/167

CPC classification number: H01L29/785 ,  H01L29/167

Abstract: Contacts to p-type source/drain regions comprise a boride, indium, or gallium metal compound layer. The boride, indium, or gallium metal compound layers can aid in forming thermally stable low resistance contacts. A boride, indium, or gallium metal compound layer is positioned between the source/drain region and the contact metal layer. A boride, indium, or gallium metal compound layer can be used in contacts contacting p-type source/drain regions comprising boron, indium, or gallium as the primary dopant, respectively. The boride, indium, or gallium metal compound layers prevent diffusion of boron, indium, or gallium from the source/drain region into the metal contact layer and dopant deactivation in the source/drain region due to annealing and other high-temperature processing steps that occur after contact formation. Boride, indium, or gallium metal contact layers can also reduce the amount of silicide that forms in source/drain regions during processing by limiting contact metal diffusion into source/drain regions.

公开(公告)号：US20230187553A1

公开(公告)日：2023-06-15

申请号：US17546461

申请日：2021-12-09

Applicant: Intel Corporation

Inventor： Arnab Sen Gupta ,  Gilbert W. Dewey ,  Siddharth Chouksey ,  Nazila Haratipour ,  Jack T. Kavalieros ,  Matthew V. Metz ,  Scott B. Clendenning ,  Jason C. Retasket ,  Edward O. Johnson, JR.

IPC: H01L29/786 ,  H01L29/66

CPC classification number: H01L29/78618 ,  H01L29/78696 ,  H01L29/66742

Abstract: Described herein are integrated circuit devices with source and drain (S/D) contacts with barrier regions. The S/D contacts conduct current to and from semiconductor devices, e.g., to the source and drain regions of a transistor. The barrier regions are formed between the S/D region and an inner conductive structure and reduce the Schottky barrier height between the S/D region and the contact. The barrier regions may include one or more carbon layers and one or more metal layers. A metal layer may include niobium, tantalum, aluminum, or titanium.

公开(公告)号：US20220199833A1

公开(公告)日：2022-06-23

申请号：US17133197

申请日：2020-12-23

Applicant: Intel Corporation

Inventor： Shriram Shivaraman ,  Uygar Avci ,  Ashish Verma Penumatcha ,  Nazila Haratipour ,  Seung Hoon Sung ,  Sou-Chi Chang

IPC: H01L29/78 ,  H01L21/28 ,  H01L29/66 ,  H01L27/1159 ,  H01L29/51

Abstract: A memory device structure includes a transistor structure including a gate electrode over a top surface of a fin and adjacent to a sidewall of the fin, a source structure coupled to a first region of the fin and a drain structure coupled to a second region of the fin, where the gate electrode is between the first and the second region. A gate dielectric layer is between the fin and the gate electrode. The memory device structure further includes a capacitor coupled with the transistor structure, the capacitor includes the gate electrode, a ferroelectric layer on a substantially planar uppermost surface of the gate electrode and a word line on the ferroelectric layer.